[Keyboard] Fix matrix issues with Promethium (#13648)

keyboards/handwired/promethium/config.h

@@ -31,12 +31,15 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
 /* key matrix size */
 #define MATRIX_COLS  6
-#define MATRIX_ROWS 3
+#define MATRIX_ROWS  9
 
 /* default pin-out */
-#define MATRIX_COL_PINS { F4, F1, F0, D6, D0, D1 }
-#define MATRIX_ROW_PINS { F5, F6, F7 }
-#define TRACKPOINT_PINS { B7, B6, D7 }
+#define MATRIX_COL_PINS \
+    { F4, F1, F0, D6, D0, D1 }
+#define MATRIX_ROW_PINS \
+    { F5, F6, F7, NO_PIN, NO_PIN, NO_PIN, NO_PIN, NO_PIN, NO_PIN }
+#define TRACKPOINT_PINS \
+    { B7, B6, D7 }
 #define UNUSED_PINS
 
 /*
@@ -90,9 +93,7 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //#define FORCE_NKRO
 
 /* key combination for command */
-#define IS_COMMAND() ( \
-    get_mods() == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT) | MOD_BIT(KC_LCTRL) | MOD_BIT(KC_RCTRL)) \
-)
+#define IS_COMMAND()         (get_mods() == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT) | MOD_BIT(KC_LCTRL) | MOD_BIT(KC_RCTRL)))
 
 /* control how magic key switches layers */
 //#define MAGIC_KEY_SWITCH_LAYER_WITH_FKEYS  true
@@ -268,14 +269,16 @@ enum led_sequence {
 #    define PS2_DATA_DDR   DDRD
 #    define PS2_DATA_BIT   2
 
-#define PS2_INT_INIT()  do {    \
-    EICRA |= ((1<<ISC31) |      \
-              (0<<ISC30));      \
+#    define PS2_INT_INIT()                          \
+        do {                                        \
+            EICRA |= ((1 << ISC31) | (0 << ISC30)); \
         } while (0)
-#define PS2_INT_ON()  do {      \
+#    define PS2_INT_ON()          \
+        do {                      \
             EIMSK |= (1 << INT3); \
         } while (0)
-#define PS2_INT_OFF() do {      \
+#    define PS2_INT_OFF()          \
+        do {                       \
             EIMSK &= ~(1 << INT3); \
         } while (0)
 #    define PS2_INT_VECT INT3_vect
@@ -295,29 +298,27 @@ enum led_sequence {
 
 /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
 /* set DDR of CLOCK as input to be slave */
-#define PS2_USART_INIT() do {   \
+#    define PS2_USART_INIT()                                                                         \
+        do {                                                                                         \
             PS2_CLOCK_DDR &= ~(1 << PS2_CLOCK_BIT);                                                  \
             PS2_DATA_DDR &= ~(1 << PS2_DATA_BIT);                                                    \
-    UCSR1C = ((1 << UMSEL10) |  \
-              (3 << UPM10)   |  \
-              (0 << USBS1)   |  \
-              (3 << UCSZ10)  |  \
-              (0 << UCPOL1));   \
+            UCSR1C = ((1 << UMSEL10) | (3 << UPM10) | (0 << USBS1) | (3 << UCSZ10) | (0 << UCPOL1)); \
             UCSR1A = 0;                                                                              \
             UBRR1H = 0;                                                                              \
             UBRR1L = 0;                                                                              \
         } while (0)
-#define PS2_USART_RX_INT_ON() do {  \
-    UCSR1B = ((1 << RXCIE1) |       \
-              (1 << RXEN1));        \
+#    define PS2_USART_RX_INT_ON()                    \
+        do {                                         \
+            UCSR1B = ((1 << RXCIE1) | (1 << RXEN1)); \
         } while (0)
-#define PS2_USART_RX_POLL_ON() do { \
+#    define PS2_USART_RX_POLL_ON() \
+        do {                       \
             UCSR1B = (1 << RXEN1); \
         } while (0)
-#define PS2_USART_OFF() do {    \
+#    define PS2_USART_OFF()                           \
+        do {                                          \
             UCSR1C = 0;                               \
-    UCSR1B &= ~((1 << RXEN1) |  \
-                (1 << TXEN1));  \
+            UCSR1B &= ~((1 << RXEN1) | (1 << TXEN1)); \
         } while (0)
 #    define PS2_USART_RX_READY (UCSR1A & (1 << RXC1))
 #    define PS2_USART_RX_DATA  UDR1