hailey
/
qmk_firmware
mirror of https://github.com/hailey/qmk_firmware.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Initial work for consolidation of ChibiOS platform files (#8327)

Browse Source 
* Initial work for consolidation of board files and default ChibiOS configs.

* Migrate F401/F411 black pills for testing.

* Add early init bootloader jump flag.

* Add support for I2C in order to use i2c_scanner keymap.

* Add F401/F411 HSE bypass to get things booting.

* Exempt "hooked" ChibiOS conf files from updater script.

* Fix up ordering for bootloader_defs file check.

* Match previous $(KEYBOARD_PATHS) value for Proton-C, updated for all board configs.
pre-develop-merge-nov20
Nick Brassel 5 years ago committed by James Young
parent 5cc3ab38c9
commit 385d49cc39
69 changed files with 2563 additions and 8236 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 9
      build_keyboard.mk
  2. 250
      drivers/boards/BLACKPILL_STM32_F401/board.c
  3. 568
      drivers/boards/BLACKPILL_STM32_F401/board.h
  4. 1193
      drivers/boards/BLACKPILL_STM32_F401/cfg/board.chcfg
  5. 15
      drivers/boards/BLACKPILL_STM32_F401/cfg/board.fmpp
  6. 250
      drivers/boards/BLACKPILL_STM32_F411/board.c
  7. 583
      drivers/boards/BLACKPILL_STM32_F411/board.h
  8. 1193
      drivers/boards/BLACKPILL_STM32_F411/cfg/board.chcfg
  9. 15
      drivers/boards/BLACKPILL_STM32_F411/cfg/board.fmpp
  10. 703
      drivers/boards/GENERIC_STM32_F072XB/cfg/board.chcfg
  11. 15
      drivers/boards/GENERIC_STM32_F072XB/cfg/board.fmpp
  12. 5
      drivers/boards/GENERIC_STM32_F303XC/board.mk
  13. 5
      drivers/boards/IC_TEENSY_3_1/board.mk
  14. 5
      drivers/boards/STM32_F103_STM32DUINO/board.mk
  15. 537
      keyboards/handwired/onekey/blackpill_f401/halconf.h
  16. 264
      keyboards/handwired/onekey/blackpill_f401/mcuconf.h
  17. 537
      keyboards/handwired/onekey/blackpill_f411/halconf.h
  18. 264
      keyboards/handwired/onekey/blackpill_f411/mcuconf.h
  19. 268
      keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.c
  20. 5
      keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.mk
  21. 896
      keyboards/vinta/boards/GENERIC_STM32_F042X6/board.h
  22. 5
      keyboards/vinta/boards/GENERIC_STM32_F042X6/board.mk
  23. 7
      keyboards/vinta/bootloader_defs.h
  24. 4
      lib/python/qmk/cli/cformat.py
  25. 9
      platforms/chibios/BLACKPILL_STM32_F401/board/board.mk
  26. 20
      platforms/chibios/BLACKPILL_STM32_F401/configs/board.h
  27. 0
      platforms/chibios/BLACKPILL_STM32_F401/configs/chconf.h
  28. 23
      platforms/chibios/BLACKPILL_STM32_F401/configs/config.h
  29. 525
      platforms/chibios/BLACKPILL_STM32_F401/configs/halconf.h
  30. 253
      platforms/chibios/BLACKPILL_STM32_F401/configs/mcuconf.h
  31. 9
      platforms/chibios/BLACKPILL_STM32_F411/board/board.mk
  32. 20
      platforms/chibios/BLACKPILL_STM32_F411/configs/board.h
  33. 0
      platforms/chibios/BLACKPILL_STM32_F411/configs/chconf.h
  34. 23
      platforms/chibios/BLACKPILL_STM32_F411/configs/config.h
  35. 525
      platforms/chibios/BLACKPILL_STM32_F411/configs/halconf.h
  36. 253
      platforms/chibios/BLACKPILL_STM32_F411/configs/mcuconf.h
  37. 3
      platforms/chibios/GENERIC_STM32_F042X6/board/board.c
  38. 0
      platforms/chibios/GENERIC_STM32_F042X6/board/board.h
  39. 4
      platforms/chibios/GENERIC_STM32_F042X6/board/board.mk
  40. 0
      platforms/chibios/GENERIC_STM32_F042X6/configs/bootloader_defs.h
  41. 0
      platforms/chibios/GENERIC_STM32_F072XB/board/board.c
  42. 0
      platforms/chibios/GENERIC_STM32_F072XB/board/board.h
  43. 4
      platforms/chibios/GENERIC_STM32_F072XB/board/board.mk
  44. 0
      platforms/chibios/GENERIC_STM32_F072XB/configs/bootloader_defs.h
  45. 2
      platforms/chibios/GENERIC_STM32_F303XC/board/board.c
  46. 0
      platforms/chibios/GENERIC_STM32_F303XC/board/board.h
  47. 4
      platforms/chibios/GENERIC_STM32_F303XC/board/board.mk
  48. 0
      platforms/chibios/GENERIC_STM32_F303XC/configs/bootloader_defs.h
  49. 362
      platforms/chibios/GENERIC_STM32_F303XC/configs/chconf.h
  50. 339
      platforms/chibios/GENERIC_STM32_F303XC/configs/halconf.h
  51. 273
      platforms/chibios/GENERIC_STM32_F303XC/configs/mcuconf.h
  52. 9
      platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk
  53. 0
      platforms/chibios/IC_TEENSY_3_1/board/board.c
  54. 0
      platforms/chibios/IC_TEENSY_3_1/board/board.h
  55. 9
      platforms/chibios/IC_TEENSY_3_1/board/board.mk
  56. 3
      platforms/chibios/STM32_F103_STM32DUINO/board/board.c
  57. 0
      platforms/chibios/STM32_F103_STM32DUINO/board/board.h
  58. 9
      platforms/chibios/STM32_F103_STM32DUINO/board/board.mk
  59. 20
      platforms/chibios/keyboard-config-templates/board.h
  60. 20
      platforms/chibios/keyboard-config-templates/chconf.h
  61. 20
      platforms/chibios/keyboard-config-templates/halconf.h
  62. 21
      platforms/chibios/keyboard-config-templates/mcuconf.h
  63. 0
      platforms/chibios/ld/MKL26Z64.ld
  64. 0
      platforms/chibios/ld/STM32F103x8_stm32duino_bootloader.ld
  65. 273
      quantum/stm32/mcuconf.h
  66. 47
      quantum/stm32/proton_c.mk
  67. 113
      tmk_core/chibios.mk
  68. 6
      util/chibios-upgrader.sh
  69. 2
      util/travis_compiled_push.sh

9
build_keyboard.mk
Unescape View File

@ -16,7 +16,6 @@ include common.mk
KEYBOARD_FILESAFE := $(subst /,_,$(KEYBOARD))
TARGET ?= $(KEYBOARD_FILESAFE)_$(KEYMAP)
KEYBOARD_OUTPUT := $(BUILD_DIR)/obj_$(KEYBOARD_FILESAFE)
STM32_PATH := quantum/stm32
# Force expansion
TARGET := $(TARGET)
@ -138,7 +137,7 @@ endif
ifeq ($(strip $(CONVERT_TO_PROTON_C)), yes)
TARGET := $(TARGET)_proton_c
include $(STM32_PATH)/proton_c.mk
include platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk
OPT_DEFS += -DCONVERT_TO_PROTON_C
endif
@ -148,12 +147,6 @@ endif
include quantum/mcu_selection.mk
ifdef MCU_FAMILY
OPT_DEFS += -DQMK_STM32
KEYBOARD_PATHS += $(STM32_PATH)
endif
# Find all the C source files to be compiled in subfolders.
KEYBOARD_SRC :=

250
drivers/boards/BLACKPILL_STM32_F401/board.c
Unescape View File

@ -1,250 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#include "stm32_gpio.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief Type of STM32 GPIO port setup.
*/
typedef struct {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
/**
* @brief Type of STM32 GPIO initialization data.
*/
typedef struct {
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
gpio_setup_t PFData;
#endif
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
gpio_setup_t PGData;
#endif
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
gpio_setup_t PHData;
#endif
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
gpio_setup_t PIData;
#endif
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
gpio_setup_t PJData;
#endif
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
gpio_setup_t PKData;
#endif
} gpio_config_t;
/**
* @brief STM32 GPIO static initialization data.
*/
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
#endif
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB1(STM32_GPIO_EN_MASK);
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
#if STM32_HAS_GPIOF
gpio_init(GPIOF, &gpio_default_config.PFData);
#endif
#if STM32_HAS_GPIOG
gpio_init(GPIOG, &gpio_default_config.PGData);
#endif
#if STM32_HAS_GPIOH
gpio_init(GPIOH, &gpio_default_config.PHData);
#endif
#if STM32_HAS_GPIOI
gpio_init(GPIOI, &gpio_default_config.PIData);
#endif
#if STM32_HAS_GPIOJ
gpio_init(GPIOJ, &gpio_default_config.PJData);
#endif
#if STM32_HAS_GPIOK
gpio_init(GPIOK, &gpio_default_config.PKData);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {}
/**
* @brief Early initialization code.
* @details GPIO ports and system clocks are initialized before everything
* else.
*/
void __early_init(void) {
enter_bootloader_mode_if_requested();
stm32_gpio_init();
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {}

568
drivers/boards/BLACKPILL_STM32_F401/board.h
Unescape View File

@ -1,568 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* Setup for STM32F401CCU6 black pill board.
*/
/*
* Board identifier.
*/
#define BOARD_BLACKPILL_STM32_F401
#define BOARD_NAME "STM32F401CCU6 blackpill"
/*
* Allow Board to boot USB without extra A9 hardware/software config
*/
#define BOARD_OTG_NOVBUSSENS 1
/*
* Board oscillators-related settings.
*/
#if !defined(STM32_LSECLK)
# define STM32_LSECLK 32768U
#endif
#if !defined(STM32_HSECLK)
# define STM32_HSECLK 25000000U
#endif
/*
* Board voltages.
* Required for performance limits calculation.
*/
#define STM32_VDD 300U
/*
* MCU type as defined in the ST header.
*/
#define STM32F401xC
/*
* IO pins assignments.
*/
#define GPIOA_BUTTON 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_CS43L22_LRCK 4U
#define GPIOA_L3GD20_SCL 5U
#define GPIOA_L3GD20_SD0 6U
#define GPIOA_L3GD20_SDI 7U
#define GPIOA_PIN8 8U
#define GPIOA_VBUS_FS 9U
#define GPIOA_OTG_FS_ID 10U
#define GPIOA_OTG_FS_DM 11U
#define GPIOA_OTG_FS_DP 12U
#define GPIOA_SWDIO 13U
#define GPIOA_SWCLK 14U
#define GPIOA_PIN15 15U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_SWO 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_LSM303DLHC_SCL 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_LSM303DLHC_SDA 9U
#define GPIOB_MP45DT02_CLK_IN 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOC_OTG_FS_POWER_ON 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_CS43L22_AIN4x 3U
#define GPIOC_MP45DT02_PDM_OUT 3U
#define GPIOC_PIN4 4U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_CS43L22_MCLK 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_CS43L22_SCLK 10U
#define GPIOC_PIN11 11U
#define GPIOC_CS43L22_SDIN 12U
#define GPIOC_PIN13 13U
#define GPIOC_OSC32_IN 14U
#define GPIOC_OSC32_OUT 15U
#define GPIOD_PIN0 0U
#define GPIOD_PIN1 1U
#define GPIOD_PIN2 2U
#define GPIOD_PIN3 3U
#define GPIOD_CS43L22_RESET 4U
#define GPIOD_OverCurrent 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_LED4 12U
#define GPIOD_LED3 13U
#define GPIOD_LED5 14U
#define GPIOD_LED6 15U
#define GPIOE_L3GD20_INT1 0U
#define GPIOE_L3GD20_INT2 1U
#define GPIOE_LSM303DLHC_DRDY 2U
#define GPIOE_L3GD20_CS 3U
#define GPIOE_LSM303DLHC_INT1 4U
#define GPIOE_LSM303DLHC_INT2 5U
#define GPIOE_PIN6 6U
#define GPIOE_PIN7 7U
#define GPIOE_PIN8 8U
#define GPIOE_PIN9 9U
#define GPIOE_PIN10 10U
#define GPIOE_PIN11 11U
#define GPIOE_PIN12 12U
#define GPIOE_PIN13 13U
#define GPIOE_PIN14 14U
#define GPIOE_PIN15 15U
#define GPIOF_PIN0 0U
#define GPIOF_PIN1 1U
#define GPIOF_PIN2 2U
#define GPIOF_PIN3 3U
#define GPIOF_PIN4 4U
#define GPIOF_PIN5 5U
#define GPIOF_PIN6 6U
#define GPIOF_PIN7 7U
#define GPIOF_PIN8 8U
#define GPIOF_PIN9 9U
#define GPIOF_PIN10 10U
#define GPIOF_PIN11 11U
#define GPIOF_PIN12 12U
#define GPIOF_PIN13 13U
#define GPIOF_PIN14 14U
#define GPIOF_PIN15 15U
#define GPIOG_PIN0 0U
#define GPIOG_PIN1 1U
#define GPIOG_PIN2 2U
#define GPIOG_PIN3 3U
#define GPIOG_PIN4 4U
#define GPIOG_PIN5 5U
#define GPIOG_PIN6 6U
#define GPIOG_PIN7 7U
#define GPIOG_PIN8 8U
#define GPIOG_PIN9 9U
#define GPIOG_PIN10 10U
#define GPIOG_PIN11 11U
#define GPIOG_PIN12 12U
#define GPIOG_PIN13 13U
#define GPIOG_PIN14 14U
#define GPIOG_PIN15 15U
#define GPIOH_OSC_IN 0U
#define GPIOH_OSC_OUT 1U
#define GPIOH_PIN2 2U
#define GPIOH_PIN3 3U
#define GPIOH_PIN4 4U
#define GPIOH_PIN5 5U
#define GPIOH_PIN6 6U
#define GPIOH_PIN7 7U
#define GPIOH_PIN8 8U
#define GPIOH_PIN9 9U
#define GPIOH_PIN10 10U
#define GPIOH_PIN11 11U
#define GPIOH_PIN12 12U
#define GPIOH_PIN13 13U
#define GPIOH_PIN14 14U
#define GPIOH_PIN15 15U
#define GPIOI_PIN0 0U
#define GPIOI_PIN1 1U
#define GPIOI_PIN2 2U
#define GPIOI_PIN3 3U
#define GPIOI_PIN4 4U
#define GPIOI_PIN5 5U
#define GPIOI_PIN6 6U
#define GPIOI_PIN7 7U
#define GPIOI_PIN8 8U
#define GPIOI_PIN9 9U
#define GPIOI_PIN10 10U
#define GPIOI_PIN11 11U
#define GPIOI_PIN12 12U
#define GPIOI_PIN13 13U
#define GPIOI_PIN14 14U
#define GPIOI_PIN15 15U
/*
* IO lines assignments.
*/
#define LINE_BUTTON PAL_LINE(GPIOA, 0U)
#define LINE_CS43L22_LRCK PAL_LINE(GPIOA, 4U)
#define LINE_L3GD20_SCL PAL_LINE(GPIOA, 5U)
#define LINE_L3GD20_SD0 PAL_LINE(GPIOA, 6U)
#define LINE_L3GD20_SDI PAL_LINE(GPIOA, 7U)
#define LINE_VBUS_FS PAL_LINE(GPIOA, 9U)
#define LINE_OTG_FS_ID PAL_LINE(GPIOA, 10U)
#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U)
#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U)
#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
#define LINE_SWO PAL_LINE(GPIOB, 3U)
#define LINE_LSM303DLHC_SCL PAL_LINE(GPIOB, 6U)
#define LINE_LSM303DLHC_SDA PAL_LINE(GPIOB, 9U)
#define LINE_MP45DT02_CLK_IN PAL_LINE(GPIOB, 10U)
#define LINE_OTG_FS_POWER_ON PAL_LINE(GPIOC, 0U)
#define LINE_CS43L22_AIN4x PAL_LINE(GPIOC, 3U)
#define LINE_MP45DT02_PDM_OUT PAL_LINE(GPIOC, 3U)
#define LINE_CS43L22_MCLK PAL_LINE(GPIOC, 7U)
#define LINE_CS43L22_SCLK PAL_LINE(GPIOC, 10U)
#define LINE_CS43L22_SDIN PAL_LINE(GPIOC, 12U)
#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
#define LINE_CS43L22_RESET PAL_LINE(GPIOD, 4U)
#define LINE_OverCurrent PAL_LINE(GPIOD, 5U)
#define LINE_LED4 PAL_LINE(GPIOD, 12U)
#define LINE_LED3 PAL_LINE(GPIOD, 13U)
#define LINE_LED5 PAL_LINE(GPIOD, 14U)
#define LINE_LED6 PAL_LINE(GPIOD, 15U)
#define LINE_L3GD20_INT1 PAL_LINE(GPIOE, 0U)
#define LINE_L3GD20_INT2 PAL_LINE(GPIOE, 1U)
#define LINE_LSM303DLHC_DRDY PAL_LINE(GPIOE, 2U)
#define LINE_L3GD20_CS PAL_LINE(GPIOE, 3U)
#define LINE_LSM303DLHC_INT1 PAL_LINE(GPIOE, 4U)
#define LINE_LSM303DLHC_INT2 PAL_LINE(GPIOE, 5U)
#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the STM32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)*2U))
#define PIN_MODE_OUTPUT(n) (1U << ((n)*2U))
#define PIN_MODE_ALTERNATE(n) (2U << ((n)*2U))
#define PIN_MODE_ANALOG(n) (3U << ((n)*2U))
#define PIN_ODR_LOW(n) (0U << (n))
#define PIN_ODR_HIGH(n) (1U << (n))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
#define PIN_OSPEED_VERYLOW(n) (0U << ((n)*2U))
#define PIN_OSPEED_LOW(n) (1U << ((n)*2U))
#define PIN_OSPEED_MEDIUM(n) (2U << ((n)*2U))
#define PIN_OSPEED_HIGH(n) (3U << ((n)*2U))
#define PIN_PUPDR_FLOATING(n) (0U << ((n)*2U))
#define PIN_PUPDR_PULLUP(n) (1U << ((n)*2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n)*2U))
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
/*
* GPIOA setup:
*
* PA0 - BUTTON (input floating).
* PA1 - PIN1 (input pullup).
* PA2 - PIN2 (input pullup).
* PA3 - PIN3 (input pullup).
* PA4 - CS43L22_LRCK (alternate 6).
* PA5 - L3GD20_SCL (alternate 5).
* PA6 - L3GD20_SD0 (alternate 5).
* PA7 - L3GD20_SDI (alternate 5).
* PA8 - PIN8 (input pullup).
* PA9 - VBUS_FS (input floating).
* PA10 - OTG_FS_ID (alternate 10).
* PA11 - OTG_FS_DM (alternate 10).
* PA12 - OTG_FS_DP (alternate 10).
* PA13 - SWDIO (alternate 0).
* PA14 - SWCLK (alternate 0).
* PA15 - PIN15 (input pullup).
*/
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | PIN_MODE_INPUT(GPIOA_PIN1) | PIN_MODE_INPUT(GPIOA_PIN2) | PIN_MODE_INPUT(GPIOA_PIN3) | PIN_MODE_ALTERNATE(GPIOA_CS43L22_LRCK) | PIN_MODE_ALTERNATE(GPIOA_L3GD20_SCL) | PIN_MODE_ALTERNATE(GPIOA_L3GD20_SD0) | PIN_MODE_ALTERNATE(GPIOA_L3GD20_SDI) | PIN_MODE_INPUT(GPIOA_PIN8) | PIN_MODE_INPUT(GPIOA_VBUS_FS) | PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | PIN_MODE_ALTERNATE(GPIOA_SWDIO) | PIN_MODE_ALTERNATE(GPIOA_SWCLK) | PIN_MODE_INPUT(GPIOA_PIN15))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | PIN_OTYPE_PUSHPULL(GPIOA_CS43L22_LRCK) | PIN_OTYPE_PUSHPULL(GPIOA_L3GD20_SCL) | PIN_OTYPE_PUSHPULL(GPIOA_L3GD20_SD0) | PIN_OTYPE_PUSHPULL(GPIOA_L3GD20_SDI) | PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON) | PIN_OSPEED_HIGH(GPIOA_PIN1) | PIN_OSPEED_HIGH(GPIOA_PIN2) | PIN_OSPEED_HIGH(GPIOA_PIN3) | PIN_OSPEED_HIGH(GPIOA_CS43L22_LRCK) | PIN_OSPEED_HIGH(GPIOA_L3GD20_SCL) | PIN_OSPEED_HIGH(GPIOA_L3GD20_SD0) | PIN_OSPEED_HIGH(GPIOA_L3GD20_SDI) | PIN_OSPEED_HIGH(GPIOA_PIN8) | PIN_OSPEED_HIGH(GPIOA_VBUS_FS) | PIN_OSPEED_HIGH(GPIOA_OTG_FS_ID) | PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | PIN_OSPEED_HIGH(GPIOA_SWDIO) | PIN_OSPEED_HIGH(GPIOA_SWCLK) | PIN_OSPEED_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | PIN_PUPDR_PULLUP(GPIOA_PIN1) | PIN_PUPDR_PULLUP(GPIOA_PIN2) | PIN_PUPDR_PULLUP(GPIOA_PIN3) | PIN_PUPDR_FLOATING(GPIOA_CS43L22_LRCK) | PIN_PUPDR_FLOATING(GPIOA_L3GD20_SCL) | PIN_PUPDR_PULLUP(GPIOA_L3GD20_SD0) | PIN_PUPDR_PULLUP(GPIOA_L3GD20_SDI) | PIN_PUPDR_PULLUP(GPIOA_PIN8) | PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | PIN_PUPDR_FLOATING(GPIOA_SWDIO) | PIN_PUPDR_FLOATING(GPIOA_SWCLK) | PIN_PUPDR_PULLUP(GPIOA_PIN15))
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | PIN_ODR_HIGH(GPIOA_PIN1) | PIN_ODR_HIGH(GPIOA_PIN2) | PIN_ODR_HIGH(GPIOA_PIN3) | PIN_ODR_HIGH(GPIOA_CS43L22_LRCK) | PIN_ODR_HIGH(GPIOA_L3GD20_SCL) | PIN_ODR_HIGH(GPIOA_L3GD20_SD0) | PIN_ODR_HIGH(GPIOA_L3GD20_SDI) | PIN_ODR_HIGH(GPIOA_PIN8) | PIN_ODR_HIGH(GPIOA_VBUS_FS) | PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | PIN_ODR_HIGH(GPIOA_SWDIO) | PIN_ODR_HIGH(GPIOA_SWCLK) | PIN_ODR_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | PIN_AFIO_AF(GPIOA_PIN1, 0U) | PIN_AFIO_AF(GPIOA_PIN2, 0U) | PIN_AFIO_AF(GPIOA_PIN3, 0U) | PIN_AFIO_AF(GPIOA_CS43L22_LRCK, 6U) | PIN_AFIO_AF(GPIOA_L3GD20_SCL, 5U) | PIN_AFIO_AF(GPIOA_L3GD20_SD0, 5U) | PIN_AFIO_AF(GPIOA_L3GD20_SDI, 5U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | PIN_AFIO_AF(GPIOA_VBUS_FS, 0U) | PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | PIN_AFIO_AF(GPIOA_SWDIO, 0U) | PIN_AFIO_AF(GPIOA_SWCLK, 0U) | PIN_AFIO_AF(GPIOA_PIN15, 0U))
/*
* GPIOB setup:
*
* PB0 - PIN0 (input pullup).
* PB1 - PIN1 (input pullup).
* PB2 - PIN2 (input pullup).
* PB3 - SWO (alternate 0).
* PB4 - PIN4 (input pullup).
* PB5 - PIN5 (input pullup).
* PB6 - LSM303DLHC_SCL (alternate 4).
* PB7 - PIN7 (input pullup).
* PB8 - PIN8 (input pullup).
* PB9 - LSM303DLHC_SDA (alternate 4).
* PB10 - MP45DT02_CLK_IN (alternate 5).
* PB11 - PIN11 (input pullup).
* PB12 - PIN12 (input pullup).
* PB13 - PIN13 (input pullup).
* PB14 - PIN14 (input pullup).
* PB15 - PIN15 (input pullup).
*/
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | PIN_MODE_INPUT(GPIOB_PIN1) | PIN_MODE_INPUT(GPIOB_PIN2) | PIN_MODE_ALTERNATE(GPIOB_SWO) | PIN_MODE_INPUT(GPIOB_PIN4) | PIN_MODE_INPUT(GPIOB_PIN5) | PIN_MODE_ALTERNATE(GPIOB_LSM303DLHC_SCL) | PIN_MODE_INPUT(GPIOB_PIN7) | PIN_MODE_INPUT(GPIOB_PIN8) | PIN_MODE_ALTERNATE(GPIOB_LSM303DLHC_SDA) | PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) | PIN_MODE_INPUT(GPIOB_PIN11) | PIN_MODE_INPUT(GPIOB_PIN12) | PIN_MODE_INPUT(GPIOB_PIN13) | PIN_MODE_INPUT(GPIOB_PIN14) | PIN_MODE_INPUT(GPIOB_PIN15))
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | PIN_OTYPE_PUSHPULL(GPIOB_SWO) | PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | PIN_OTYPE_PUSHPULL(GPIOB_LSM303DLHC_SCL) | PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | PIN_OTYPE_PUSHPULL(GPIOB_LSM303DLHC_SDA) | PIN_OTYPE_PUSHPULL(GPIOB_MP45DT02_CLK_IN) | PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | PIN_OSPEED_HIGH(GPIOB_PIN1) | PIN_OSPEED_HIGH(GPIOB_PIN2) | PIN_OSPEED_HIGH(GPIOB_SWO) | PIN_OSPEED_HIGH(GPIOB_PIN4) | PIN_OSPEED_HIGH(GPIOB_PIN5) | PIN_OSPEED_HIGH(GPIOB_LSM303DLHC_SCL) | PIN_OSPEED_HIGH(GPIOB_PIN7) | PIN_OSPEED_HIGH(GPIOB_PIN8) | PIN_OSPEED_HIGH(GPIOB_LSM303DLHC_SDA) | PIN_OSPEED_HIGH(GPIOB_MP45DT02_CLK_IN) | PIN_OSPEED_HIGH(GPIOB_PIN11) | PIN_OSPEED_HIGH(GPIOB_PIN12) | PIN_OSPEED_HIGH(GPIOB_PIN13) | PIN_OSPEED_HIGH(GPIOB_PIN14) | PIN_OSPEED_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | PIN_PUPDR_PULLUP(GPIOB_PIN1) | PIN_PUPDR_PULLUP(GPIOB_PIN2) | PIN_PUPDR_PULLUP(GPIOB_SWO) | PIN_PUPDR_PULLUP(GPIOB_PIN4) | PIN_PUPDR_PULLUP(GPIOB_PIN5) | PIN_PUPDR_FLOATING(GPIOB_LSM303DLHC_SCL) | PIN_PUPDR_PULLUP(GPIOB_PIN7) | PIN_PUPDR_PULLUP(GPIOB_PIN8) | PIN_PUPDR_FLOATING(GPIOB_LSM303DLHC_SDA) | PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) | PIN_PUPDR_PULLUP(GPIOB_PIN11) | PIN_PUPDR_PULLUP(GPIOB_PIN12) | PIN_PUPDR_PULLUP(GPIOB_PIN13) | PIN_PUPDR_PULLUP(GPIOB_PIN14) | PIN_PUPDR_PULLUP(GPIOB_PIN15))
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | PIN_ODR_HIGH(GPIOB_PIN1) | PIN_ODR_HIGH(GPIOB_PIN2) | PIN_ODR_HIGH(GPIOB_SWO) | PIN_ODR_HIGH(GPIOB_PIN4) | PIN_ODR_HIGH(GPIOB_PIN5) | PIN_ODR_HIGH(GPIOB_LSM303DLHC_SCL) | PIN_ODR_HIGH(GPIOB_PIN7) | PIN_ODR_HIGH(GPIOB_PIN8) | PIN_ODR_HIGH(GPIOB_LSM303DLHC_SDA) | PIN_ODR_HIGH(GPIOB_MP45DT02_CLK_IN) | PIN_ODR_HIGH(GPIOB_PIN11) | PIN_ODR_HIGH(GPIOB_PIN12) | PIN_ODR_HIGH(GPIOB_PIN13) | PIN_ODR_HIGH(GPIOB_PIN14) | PIN_ODR_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | PIN_AFIO_AF(GPIOB_PIN1, 0U) | PIN_AFIO_AF(GPIOB_PIN2, 0U) | PIN_AFIO_AF(GPIOB_SWO, 0U) | PIN_AFIO_AF(GPIOB_PIN4, 0U) | PIN_AFIO_AF(GPIOB_PIN5, 0U) | PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 4U) | PIN_AFIO_AF(GPIOB_PIN7, 0U))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 4U) | PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) | PIN_AFIO_AF(GPIOB_PIN11, 0U) | PIN_AFIO_AF(GPIOB_PIN12, 0U) | PIN_AFIO_AF(GPIOB_PIN13, 0U) | PIN_AFIO_AF(GPIOB_PIN14, 0U) | PIN_AFIO_AF(GPIOB_PIN15, 0U))
/*
* GPIOC setup:
*
* PC0 - OTG_FS_POWER_ON (output pushpull maximum).
* PC1 - PIN1 (input pullup).
* PC2 - PIN2 (input pullup).
* PC3 - CS43L22_AIN4x MP45DT02_PDM_OUT(alternate 5).
* PC4 - PIN4 (input pullup).
* PC5 - PIN5 (input pullup).
* PC6 - PIN6 (input pullup).
* PC7 - CS43L22_MCLK (alternate 6).
* PC8 - PIN8 (input pullup).
* PC9 - PIN9 (input pullup).
* PC10 - CS43L22_SCLK (alternate 6).
* PC11 - PIN11 (input pullup).
* PC12 - CS43L22_SDIN (alternate 6).
* PC13 - PIN13 (input pullup).
* PC14 - OSC32_IN (input floating).
* PC15 - OSC32_OUT (input floating).
*/
#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) | PIN_MODE_INPUT(GPIOC_PIN1) | PIN_MODE_INPUT(GPIOC_PIN2) | PIN_MODE_ALTERNATE(GPIOC_CS43L22_AIN4x) | PIN_MODE_INPUT(GPIOC_PIN4) | PIN_MODE_INPUT(GPIOC_PIN5) | PIN_MODE_INPUT(GPIOC_PIN6) | PIN_MODE_ALTERNATE(GPIOC_CS43L22_MCLK) | PIN_MODE_INPUT(GPIOC_PIN8) | PIN_MODE_INPUT(GPIOC_PIN9) | PIN_MODE_ALTERNATE(GPIOC_CS43L22_SCLK) | PIN_MODE_INPUT(GPIOC_PIN11) | PIN_MODE_ALTERNATE(GPIOC_CS43L22_SDIN) | PIN_MODE_INPUT(GPIOC_PIN13) | PIN_MODE_INPUT(GPIOC_OSC32_IN) | PIN_MODE_INPUT(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) | PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_AIN4x) | PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_MCLK) | PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_SCLK) | PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | PIN_OTYPE_PUSHPULL(GPIOC_CS43L22_SDIN) | PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_OTG_FS_POWER_ON) | PIN_OSPEED_HIGH(GPIOC_PIN1) | PIN_OSPEED_HIGH(GPIOC_PIN2) | PIN_OSPEED_HIGH(GPIOC_CS43L22_AIN4x) | PIN_OSPEED_HIGH(GPIOC_PIN4) | PIN_OSPEED_HIGH(GPIOC_PIN5) | PIN_OSPEED_HIGH(GPIOC_PIN6) | PIN_OSPEED_HIGH(GPIOC_CS43L22_MCLK) | PIN_OSPEED_HIGH(GPIOC_PIN8) | PIN_OSPEED_HIGH(GPIOC_PIN9) | PIN_OSPEED_HIGH(GPIOC_CS43L22_SCLK) | PIN_OSPEED_HIGH(GPIOC_PIN11) | PIN_OSPEED_HIGH(GPIOC_CS43L22_SDIN) | PIN_OSPEED_HIGH(GPIOC_PIN13) | PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_OTG_FS_POWER_ON) | PIN_PUPDR_PULLUP(GPIOC_PIN1) | PIN_PUPDR_PULLUP(GPIOC_PIN2) | PIN_PUPDR_FLOATING(GPIOC_CS43L22_AIN4x) | PIN_PUPDR_PULLUP(GPIOC_PIN4) | PIN_PUPDR_PULLUP(GPIOC_PIN5) | PIN_PUPDR_PULLUP(GPIOC_PIN6) | PIN_PUPDR_PULLUP(GPIOC_CS43L22_MCLK) | PIN_PUPDR_PULLUP(GPIOC_PIN8) | PIN_PUPDR_PULLUP(GPIOC_PIN9) | PIN_PUPDR_PULLUP(GPIOC_CS43L22_SCLK) | PIN_PUPDR_PULLUP(GPIOC_PIN11) | PIN_PUPDR_PULLUP(GPIOC_CS43L22_SDIN) | PIN_PUPDR_PULLUP(GPIOC_PIN13) | PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | PIN_ODR_HIGH(GPIOC_PIN1) | PIN_ODR_HIGH(GPIOC_PIN2) | PIN_ODR_HIGH(GPIOC_CS43L22_AIN4x) | PIN_ODR_HIGH(GPIOC_PIN4) | PIN_ODR_HIGH(GPIOC_PIN5) | PIN_ODR_HIGH(GPIOC_PIN6) | PIN_ODR_HIGH(GPIOC_CS43L22_MCLK) | PIN_ODR_HIGH(GPIOC_PIN8) | PIN_ODR_HIGH(GPIOC_PIN9) | PIN_ODR_HIGH(GPIOC_CS43L22_SCLK) | PIN_ODR_HIGH(GPIOC_PIN11) | PIN_ODR_HIGH(GPIOC_CS43L22_SDIN) | PIN_ODR_HIGH(GPIOC_PIN13) | PIN_ODR_HIGH(GPIOC_OSC32_IN) | PIN_ODR_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0U) | PIN_AFIO_AF(GPIOC_PIN1, 0U) | PIN_AFIO_AF(GPIOC_PIN2, 0U) | PIN_AFIO_AF(GPIOC_CS43L22_AIN4x, 5U) | PIN_AFIO_AF(GPIOC_PIN4, 0U) | PIN_AFIO_AF(GPIOC_PIN5, 0U) | PIN_AFIO_AF(GPIOC_PIN6, 0U) | PIN_AFIO_AF(GPIOC_CS43L22_MCLK, 6U))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | PIN_AFIO_AF(GPIOC_PIN9, 0U) | PIN_AFIO_AF(GPIOC_CS43L22_SCLK, 6U) | PIN_AFIO_AF(GPIOC_PIN11, 0U) | PIN_AFIO_AF(GPIOC_CS43L22_SDIN, 6U) | PIN_AFIO_AF(GPIOC_PIN13, 0U) | PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
/*
* GPIOD setup:
*
* PD0 - PIN0 (input pullup).
* PD1 - PIN1 (input pullup).
* PD2 - PIN2 (input pullup).
* PD3 - PIN3 (input pullup).
* PD4 - CS43L22_RESET (output pushpull maximum).
* PD5 - OverCurrent (input floating).
* PD6 - PIN6 (input pullup).
* PD7 - PIN7 (input pullup).
* PD8 - PIN8 (input pullup).
* PD9 - PIN9 (input pullup).
* PD10 - PIN10 (input pullup).
* PD11 - PIN11 (input pullup).
* PD12 - LED4 (output pushpull maximum).
* PD13 - LED3 (output pushpull maximum).
* PD14 - LED5 (output pushpull maximum).
* PD15 - LED6 (output pushpull maximum).
*/
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | PIN_MODE_INPUT(GPIOD_PIN1) | PIN_MODE_INPUT(GPIOD_PIN2) | PIN_MODE_INPUT(GPIOD_PIN3) | PIN_MODE_OUTPUT(GPIOD_CS43L22_RESET) | PIN_MODE_INPUT(GPIOD_OverCurrent) | PIN_MODE_INPUT(GPIOD_PIN6) | PIN_MODE_INPUT(GPIOD_PIN7) | PIN_MODE_INPUT(GPIOD_PIN8) | PIN_MODE_INPUT(GPIOD_PIN9) | PIN_MODE_INPUT(GPIOD_PIN10) | PIN_MODE_INPUT(GPIOD_PIN11) | PIN_MODE_OUTPUT(GPIOD_LED4) | PIN_MODE_OUTPUT(GPIOD_LED3) | PIN_MODE_OUTPUT(GPIOD_LED5) | PIN_MODE_OUTPUT(GPIOD_LED6))
#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | PIN_OTYPE_PUSHPULL(GPIOD_CS43L22_RESET) | PIN_OTYPE_PUSHPULL(GPIOD_OverCurrent) | PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | PIN_OTYPE_PUSHPULL(GPIOD_LED4) | PIN_OTYPE_PUSHPULL(GPIOD_LED3) | PIN_OTYPE_PUSHPULL(GPIOD_LED5) | PIN_OTYPE_PUSHPULL(GPIOD_LED6))
#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | PIN_OSPEED_HIGH(GPIOD_PIN1) | PIN_OSPEED_HIGH(GPIOD_PIN2) | PIN_OSPEED_HIGH(GPIOD_PIN3) | PIN_OSPEED_HIGH(GPIOD_CS43L22_RESET) | PIN_OSPEED_HIGH(GPIOD_OverCurrent) | PIN_OSPEED_HIGH(GPIOD_PIN6) | PIN_OSPEED_HIGH(GPIOD_PIN7) | PIN_OSPEED_HIGH(GPIOD_PIN8) | PIN_OSPEED_HIGH(GPIOD_PIN9) | PIN_OSPEED_HIGH(GPIOD_PIN10) | PIN_OSPEED_HIGH(GPIOD_PIN11) | PIN_OSPEED_HIGH(GPIOD_LED4) | PIN_OSPEED_HIGH(GPIOD_LED3) | PIN_OSPEED_HIGH(GPIOD_LED5) | PIN_OSPEED_HIGH(GPIOD_LED6))
#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | PIN_PUPDR_PULLUP(GPIOD_PIN1) | PIN_PUPDR_PULLUP(GPIOD_PIN2) | PIN_PUPDR_PULLUP(GPIOD_PIN3) | PIN_PUPDR_PULLUP(GPIOD_CS43L22_RESET) | PIN_PUPDR_FLOATING(GPIOD_OverCurrent) | PIN_PUPDR_PULLUP(GPIOD_PIN6) | PIN_PUPDR_PULLUP(GPIOD_PIN7) | PIN_PUPDR_PULLUP(GPIOD_PIN8) | PIN_PUPDR_PULLUP(GPIOD_PIN9) | PIN_PUPDR_PULLUP(GPIOD_PIN10) | PIN_PUPDR_PULLUP(GPIOD_PIN11) | PIN_PUPDR_FLOATING(GPIOD_LED4) | PIN_PUPDR_FLOATING(GPIOD_LED3) | PIN_PUPDR_FLOATING(GPIOD_LED5) | PIN_PUPDR_FLOATING(GPIOD_LED6))
#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | PIN_ODR_HIGH(GPIOD_PIN1) | PIN_ODR_HIGH(GPIOD_PIN2) | PIN_ODR_HIGH(GPIOD_PIN3) | PIN_ODR_HIGH(GPIOD_CS43L22_RESET) | PIN_ODR_HIGH(GPIOD_OverCurrent) | PIN_ODR_HIGH(GPIOD_PIN6) | PIN_ODR_HIGH(GPIOD_PIN7) | PIN_ODR_HIGH(GPIOD_PIN8) | PIN_ODR_HIGH(GPIOD_PIN9) | PIN_ODR_HIGH(GPIOD_PIN10) | PIN_ODR_HIGH(GPIOD_PIN11) | PIN_ODR_LOW(GPIOD_LED4) | PIN_ODR_LOW(GPIOD_LED3) | PIN_ODR_LOW(GPIOD_LED5) | PIN_ODR_LOW(GPIOD_LED6))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | PIN_AFIO_AF(GPIOD_PIN1, 0U) | PIN_AFIO_AF(GPIOD_PIN2, 0U) | PIN_AFIO_AF(GPIOD_PIN3, 0U) | PIN_AFIO_AF(GPIOD_CS43L22_RESET, 0U) | PIN_AFIO_AF(GPIOD_OverCurrent, 0U) | PIN_AFIO_AF(GPIOD_PIN6, 0U) | PIN_AFIO_AF(GPIOD_PIN7, 0U))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | PIN_AFIO_AF(GPIOD_PIN9, 0U) | PIN_AFIO_AF(GPIOD_PIN10, 0U) | PIN_AFIO_AF(GPIOD_PIN11, 0U) | PIN_AFIO_AF(GPIOD_LED4, 0U) | PIN_AFIO_AF(GPIOD_LED3, 0U) | PIN_AFIO_AF(GPIOD_LED5, 0U) | PIN_AFIO_AF(GPIOD_LED6, 0U))
/*
* GPIOE setup:
*
* PE0 - L3GD20_INT1 (input pullup).
* PE1 - L3GD20_INT2 (input pullup).
* PE2 - LSM303DLHC_DRDY (input floating).
* PE3 - L3GD20_CS (output pushpull maximum).
* PE4 - LSM303DLHC_INT1 (output pushpull maximum).
* PE5 - LSM303DLHC_INT2 (output pushpull maximum).
* PE6 - PIN6 (input pullup).
* PE7 - PIN7 (input pullup).
* PE8 - PIN8 (input pullup).
* PE9 - PIN9 (input pullup).
* PE10 - PIN10 (input pullup).
* PE11 - PIN11 (input pullup).
* PE12 - PIN12 (input pullup).
* PE13 - PIN13 (input pullup).
* PE14 - PIN14 (input pullup).
* PE15 - PIN15 (input pullup).
*/
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_L3GD20_INT1) | PIN_MODE_INPUT(GPIOE_L3GD20_INT2) | PIN_MODE_INPUT(GPIOE_LSM303DLHC_DRDY) | PIN_MODE_OUTPUT(GPIOE_L3GD20_CS) | PIN_MODE_OUTPUT(GPIOE_LSM303DLHC_INT1) | PIN_MODE_OUTPUT(GPIOE_LSM303DLHC_INT2) | PIN_MODE_INPUT(GPIOE_PIN6) | PIN_MODE_INPUT(GPIOE_PIN7) | PIN_MODE_INPUT(GPIOE_PIN8) | PIN_MODE_INPUT(GPIOE_PIN9) | PIN_MODE_INPUT(GPIOE_PIN10) | PIN_MODE_INPUT(GPIOE_PIN11) | PIN_MODE_INPUT(GPIOE_PIN12) | PIN_MODE_INPUT(GPIOE_PIN13) | PIN_MODE_INPUT(GPIOE_PIN14) | PIN_MODE_INPUT(GPIOE_PIN15))
#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT1) | PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT2) | PIN_OTYPE_PUSHPULL(GPIOE_LSM303DLHC_DRDY) | PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_CS) | PIN_OTYPE_PUSHPULL(GPIOE_LSM303DLHC_INT1) | PIN_OTYPE_PUSHPULL(GPIOE_LSM303DLHC_INT2) | PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_L3GD20_INT1) | PIN_OSPEED_HIGH(GPIOE_L3GD20_INT2) | PIN_OSPEED_HIGH(GPIOE_LSM303DLHC_DRDY) | PIN_OSPEED_HIGH(GPIOE_L3GD20_CS) | PIN_OSPEED_HIGH(GPIOE_LSM303DLHC_INT1) | PIN_OSPEED_HIGH(GPIOE_LSM303DLHC_INT2) | PIN_OSPEED_HIGH(GPIOE_PIN6) | PIN_OSPEED_HIGH(GPIOE_PIN7) | PIN_OSPEED_HIGH(GPIOE_PIN8) | PIN_OSPEED_HIGH(GPIOE_PIN9) | PIN_OSPEED_HIGH(GPIOE_PIN10) | PIN_OSPEED_HIGH(GPIOE_PIN11) | PIN_OSPEED_HIGH(GPIOE_PIN12) | PIN_OSPEED_HIGH(GPIOE_PIN13) | PIN_OSPEED_HIGH(GPIOE_PIN14) | PIN_OSPEED_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT1) | PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT2) | PIN_PUPDR_FLOATING(GPIOE_LSM303DLHC_DRDY) | PIN_PUPDR_PULLUP(GPIOE_L3GD20_CS) | PIN_PUPDR_PULLUP(GPIOE_LSM303DLHC_INT1) | PIN_PUPDR_PULLUP(GPIOE_LSM303DLHC_INT2) | PIN_PUPDR_PULLUP(GPIOE_PIN6) | PIN_PUPDR_PULLUP(GPIOE_PIN7) | PIN_PUPDR_PULLUP(GPIOE_PIN8) | PIN_PUPDR_PULLUP(GPIOE_PIN9) | PIN_PUPDR_PULLUP(GPIOE_PIN10) | PIN_PUPDR_PULLUP(GPIOE_PIN11) | PIN_PUPDR_PULLUP(GPIOE_PIN12) | PIN_PUPDR_PULLUP(GPIOE_PIN13) | PIN_PUPDR_PULLUP(GPIOE_PIN14) | PIN_PUPDR_PULLUP(GPIOE_PIN15))
#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_L3GD20_INT1) | PIN_ODR_HIGH(GPIOE_L3GD20_INT2) | PIN_ODR_HIGH(GPIOE_LSM303DLHC_DRDY) | PIN_ODR_HIGH(GPIOE_L3GD20_CS) | PIN_ODR_HIGH(GPIOE_LSM303DLHC_INT1) | PIN_ODR_HIGH(GPIOE_LSM303DLHC_INT2) | PIN_ODR_HIGH(GPIOE_PIN6) | PIN_ODR_HIGH(GPIOE_PIN7) | PIN_ODR_HIGH(GPIOE_PIN8) | PIN_ODR_HIGH(GPIOE_PIN9) | PIN_ODR_HIGH(GPIOE_PIN10) | PIN_ODR_HIGH(GPIOE_PIN11) | PIN_ODR_HIGH(GPIOE_PIN12) | PIN_ODR_HIGH(GPIOE_PIN13) | PIN_ODR_HIGH(GPIOE_PIN14) | PIN_ODR_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_L3GD20_INT1, 0U) | PIN_AFIO_AF(GPIOE_L3GD20_INT2, 0U) | PIN_AFIO_AF(GPIOE_LSM303DLHC_DRDY, 0U) | PIN_AFIO_AF(GPIOE_L3GD20_CS, 0U) | PIN_AFIO_AF(GPIOE_LSM303DLHC_INT1, 0U) | PIN_AFIO_AF(GPIOE_LSM303DLHC_INT2, 0U) | PIN_AFIO_AF(GPIOE_PIN6, 0U) | PIN_AFIO_AF(GPIOE_PIN7, 0U))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | PIN_AFIO_AF(GPIOE_PIN9, 0U) | PIN_AFIO_AF(GPIOE_PIN10, 0U) | PIN_AFIO_AF(GPIOE_PIN11, 0U) | PIN_AFIO_AF(GPIOE_PIN12, 0U) | PIN_AFIO_AF(GPIOE_PIN13, 0U) | PIN_AFIO_AF(GPIOE_PIN14, 0U) | PIN_AFIO_AF(GPIOE_PIN15, 0U))
/*
* GPIOF setup:
*
* PF0 - PIN0 (input pullup).
* PF1 - PIN1 (input pullup).
* PF2 - PIN2 (input pullup).
* PF3 - PIN3 (input pullup).
* PF4 - PIN4 (input pullup).
* PF5 - PIN5 (input pullup).
* PF6 - PIN6 (input pullup).
* PF7 - PIN7 (input pullup).
* PF8 - PIN8 (input pullup).
* PF9 - PIN9 (input pullup).
* PF10 - PIN10 (input pullup).
* PF11 - PIN11 (input pullup).
* PF12 - PIN12 (input pullup).
* PF13 - PIN13 (input pullup).
* PF14 - PIN14 (input pullup).
* PF15 - PIN15 (input pullup).
*/
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | PIN_MODE_INPUT(GPIOF_PIN1) | PIN_MODE_INPUT(GPIOF_PIN2) | PIN_MODE_INPUT(GPIOF_PIN3) | PIN_MODE_INPUT(GPIOF_PIN4) | PIN_MODE_INPUT(GPIOF_PIN5) | PIN_MODE_INPUT(GPIOF_PIN6) | PIN_MODE_INPUT(GPIOF_PIN7) | PIN_MODE_INPUT(GPIOF_PIN8) | PIN_MODE_INPUT(GPIOF_PIN9) | PIN_MODE_INPUT(GPIOF_PIN10) | PIN_MODE_INPUT(GPIOF_PIN11) | PIN_MODE_INPUT(GPIOF_PIN12) | PIN_MODE_INPUT(GPIOF_PIN13) | PIN_MODE_INPUT(GPIOF_PIN14) | PIN_MODE_INPUT(GPIOF_PIN15))
#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | PIN_OSPEED_HIGH(GPIOF_PIN1) | PIN_OSPEED_HIGH(GPIOF_PIN2) | PIN_OSPEED_HIGH(GPIOF_PIN3) | PIN_OSPEED_HIGH(GPIOF_PIN4) | PIN_OSPEED_HIGH(GPIOF_PIN5) | PIN_OSPEED_HIGH(GPIOF_PIN6) | PIN_OSPEED_HIGH(GPIOF_PIN7) | PIN_OSPEED_HIGH(GPIOF_PIN8) | PIN_OSPEED_HIGH(GPIOF_PIN9) | PIN_OSPEED_HIGH(GPIOF_PIN10) | PIN_OSPEED_HIGH(GPIOF_PIN11) | PIN_OSPEED_HIGH(GPIOF_PIN12) | PIN_OSPEED_HIGH(GPIOF_PIN13) | PIN_OSPEED_HIGH(GPIOF_PIN14) | PIN_OSPEED_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | PIN_PUPDR_PULLUP(GPIOF_PIN1) | PIN_PUPDR_PULLUP(GPIOF_PIN2) | PIN_PUPDR_PULLUP(GPIOF_PIN3) | PIN_PUPDR_PULLUP(GPIOF_PIN4) | PIN_PUPDR_PULLUP(GPIOF_PIN5) | PIN_PUPDR_PULLUP(GPIOF_PIN6) | PIN_PUPDR_PULLUP(GPIOF_PIN7) | PIN_PUPDR_PULLUP(GPIOF_PIN8) | PIN_PUPDR_PULLUP(GPIOF_PIN9) | PIN_PUPDR_PULLUP(GPIOF_PIN10) | PIN_PUPDR_PULLUP(GPIOF_PIN11) | PIN_PUPDR_PULLUP(GPIOF_PIN12) | PIN_PUPDR_PULLUP(GPIOF_PIN13) | PIN_PUPDR_PULLUP(GPIOF_PIN14) | PIN_PUPDR_PULLUP(GPIOF_PIN15))
#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | PIN_ODR_HIGH(GPIOF_PIN1) | PIN_ODR_HIGH(GPIOF_PIN2) | PIN_ODR_HIGH(GPIOF_PIN3) | PIN_ODR_HIGH(GPIOF_PIN4) | PIN_ODR_HIGH(GPIOF_PIN5) | PIN_ODR_HIGH(GPIOF_PIN6) | PIN_ODR_HIGH(GPIOF_PIN7) | PIN_ODR_HIGH(GPIOF_PIN8) | PIN_ODR_HIGH(GPIOF_PIN9) | PIN_ODR_HIGH(GPIOF_PIN10) | PIN_ODR_HIGH(GPIOF_PIN11) | PIN_ODR_HIGH(GPIOF_PIN12) | PIN_ODR_HIGH(GPIOF_PIN13) | PIN_ODR_HIGH(GPIOF_PIN14) | PIN_ODR_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | PIN_AFIO_AF(GPIOF_PIN1, 0U) | PIN_AFIO_AF(GPIOF_PIN2, 0U) | PIN_AFIO_AF(GPIOF_PIN3, 0U) | PIN_AFIO_AF(GPIOF_PIN4, 0U) | PIN_AFIO_AF(GPIOF_PIN5, 0U) | PIN_AFIO_AF(GPIOF_PIN6, 0U) | PIN_AFIO_AF(GPIOF_PIN7, 0U))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | PIN_AFIO_AF(GPIOF_PIN9, 0U) | PIN_AFIO_AF(GPIOF_PIN10, 0U) | PIN_AFIO_AF(GPIOF_PIN11, 0U) | PIN_AFIO_AF(GPIOF_PIN12, 0U) | PIN_AFIO_AF(GPIOF_PIN13, 0U) | PIN_AFIO_AF(GPIOF_PIN14, 0U) | PIN_AFIO_AF(GPIOF_PIN15, 0U))
/*
* GPIOG setup:
*
* PG0 - PIN0 (input pullup).
* PG1 - PIN1 (input pullup).
* PG2 - PIN2 (input pullup).
* PG3 - PIN3 (input pullup).
* PG4 - PIN4 (input pullup).
* PG5 - PIN5 (input pullup).
* PG6 - PIN6 (input pullup).
* PG7 - PIN7 (input pullup).
* PG8 - PIN8 (input pullup).
* PG9 - PIN9 (input pullup).
* PG10 - PIN10 (input pullup).
* PG11 - PIN11 (input pullup).
* PG12 - PIN12 (input pullup).
* PG13 - PIN13 (input pullup).
* PG14 - PIN14 (input pullup).
* PG15 - PIN15 (input pullup).
*/
#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | PIN_MODE_INPUT(GPIOG_PIN1) | PIN_MODE_INPUT(GPIOG_PIN2) | PIN_MODE_INPUT(GPIOG_PIN3) | PIN_MODE_INPUT(GPIOG_PIN4) | PIN_MODE_INPUT(GPIOG_PIN5) | PIN_MODE_INPUT(GPIOG_PIN6) | PIN_MODE_INPUT(GPIOG_PIN7) | PIN_MODE_INPUT(GPIOG_PIN8) | PIN_MODE_INPUT(GPIOG_PIN9) | PIN_MODE_INPUT(GPIOG_PIN10) | PIN_MODE_INPUT(GPIOG_PIN11) | PIN_MODE_INPUT(GPIOG_PIN12) | PIN_MODE_INPUT(GPIOG_PIN13) | PIN_MODE_INPUT(GPIOG_PIN14) | PIN_MODE_INPUT(GPIOG_PIN15))
#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | PIN_OSPEED_HIGH(GPIOG_PIN1) | PIN_OSPEED_HIGH(GPIOG_PIN2) | PIN_OSPEED_HIGH(GPIOG_PIN3) | PIN_OSPEED_HIGH(GPIOG_PIN4) | PIN_OSPEED_HIGH(GPIOG_PIN5) | PIN_OSPEED_HIGH(GPIOG_PIN6) | PIN_OSPEED_HIGH(GPIOG_PIN7) | PIN_OSPEED_HIGH(GPIOG_PIN8) | PIN_OSPEED_HIGH(GPIOG_PIN9) | PIN_OSPEED_HIGH(GPIOG_PIN10) | PIN_OSPEED_HIGH(GPIOG_PIN11) | PIN_OSPEED_HIGH(GPIOG_PIN12) | PIN_OSPEED_HIGH(GPIOG_PIN13) | PIN_OSPEED_HIGH(GPIOG_PIN14) | PIN_OSPEED_HIGH(GPIOG_PIN15))
#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | PIN_PUPDR_PULLUP(GPIOG_PIN1) | PIN_PUPDR_PULLUP(GPIOG_PIN2) | PIN_PUPDR_PULLUP(GPIOG_PIN3) | PIN_PUPDR_PULLUP(GPIOG_PIN4) | PIN_PUPDR_PULLUP(GPIOG_PIN5) | PIN_PUPDR_PULLUP(GPIOG_PIN6) | PIN_PUPDR_PULLUP(GPIOG_PIN7) | PIN_PUPDR_PULLUP(GPIOG_PIN8) | PIN_PUPDR_PULLUP(GPIOG_PIN9) | PIN_PUPDR_PULLUP(GPIOG_PIN10) | PIN_PUPDR_PULLUP(GPIOG_PIN11) | PIN_PUPDR_PULLUP(GPIOG_PIN12) | PIN_PUPDR_PULLUP(GPIOG_PIN13) | PIN_PUPDR_PULLUP(GPIOG_PIN14) | PIN_PUPDR_PULLUP(GPIOG_PIN15))
#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | PIN_ODR_HIGH(GPIOG_PIN1) | PIN_ODR_HIGH(GPIOG_PIN2) | PIN_ODR_HIGH(GPIOG_PIN3) | PIN_ODR_HIGH(GPIOG_PIN4) | PIN_ODR_HIGH(GPIOG_PIN5) | PIN_ODR_HIGH(GPIOG_PIN6) | PIN_ODR_HIGH(GPIOG_PIN7) | PIN_ODR_HIGH(GPIOG_PIN8) | PIN_ODR_HIGH(GPIOG_PIN9) | PIN_ODR_HIGH(GPIOG_PIN10) | PIN_ODR_HIGH(GPIOG_PIN11) | PIN_ODR_HIGH(GPIOG_PIN12) | PIN_ODR_HIGH(GPIOG_PIN13) | PIN_ODR_HIGH(GPIOG_PIN14) | PIN_ODR_HIGH(GPIOG_PIN15))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | PIN_AFIO_AF(GPIOG_PIN1, 0U) | PIN_AFIO_AF(GPIOG_PIN2, 0U) | PIN_AFIO_AF(GPIOG_PIN3, 0U) | PIN_AFIO_AF(GPIOG_PIN4, 0U) | PIN_AFIO_AF(GPIOG_PIN5, 0U) | PIN_AFIO_AF(GPIOG_PIN6, 0U) | PIN_AFIO_AF(GPIOG_PIN7, 0U))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | PIN_AFIO_AF(GPIOG_PIN9, 0U) | PIN_AFIO_AF(GPIOG_PIN10, 0U) | PIN_AFIO_AF(GPIOG_PIN11, 0U) | PIN_AFIO_AF(GPIOG_PIN12, 0U) | PIN_AFIO_AF(GPIOG_PIN13, 0U) | PIN_AFIO_AF(GPIOG_PIN14, 0U) | PIN_AFIO_AF(GPIOG_PIN15, 0U))
/*
* GPIOH setup:
*
* PH0 - OSC_IN (input floating).
* PH1 - OSC_OUT (input floating).
* PH2 - PIN2 (input pullup).
* PH3 - PIN3 (input pullup).
* PH4 - PIN4 (input pullup).
* PH5 - PIN5 (input pullup).
* PH6 - PIN6 (input pullup).
* PH7 - PIN7 (input pullup).
* PH8 - PIN8 (input pullup).
* PH9 - PIN9 (input pullup).
* PH10 - PIN10 (input pullup).
* PH11 - PIN11 (input pullup).
* PH12 - PIN12 (input pullup).
* PH13 - PIN13 (input pullup).
* PH14 - PIN14 (input pullup).
* PH15 - PIN15 (input pullup).
*/
#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | PIN_MODE_INPUT(GPIOH_OSC_OUT) | PIN_MODE_INPUT(GPIOH_PIN2) | PIN_MODE_INPUT(GPIOH_PIN3) | PIN_MODE_INPUT(GPIOH_PIN4) | PIN_MODE_INPUT(GPIOH_PIN5) | PIN_MODE_INPUT(GPIOH_PIN6) | PIN_MODE_INPUT(GPIOH_PIN7) | PIN_MODE_INPUT(GPIOH_PIN8) | PIN_MODE_INPUT(GPIOH_PIN9) | PIN_MODE_INPUT(GPIOH_PIN10) | PIN_MODE_INPUT(GPIOH_PIN11) | PIN_MODE_INPUT(GPIOH_PIN12) | PIN_MODE_INPUT(GPIOH_PIN13) | PIN_MODE_INPUT(GPIOH_PIN14) | PIN_MODE_INPUT(GPIOH_PIN15))
#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | PIN_OSPEED_HIGH(GPIOH_PIN2) | PIN_OSPEED_HIGH(GPIOH_PIN3) | PIN_OSPEED_HIGH(GPIOH_PIN4) | PIN_OSPEED_HIGH(GPIOH_PIN5) | PIN_OSPEED_HIGH(GPIOH_PIN6) | PIN_OSPEED_HIGH(GPIOH_PIN7) | PIN_OSPEED_HIGH(GPIOH_PIN8) | PIN_OSPEED_HIGH(GPIOH_PIN9) | PIN_OSPEED_HIGH(GPIOH_PIN10) | PIN_OSPEED_HIGH(GPIOH_PIN11) | PIN_OSPEED_HIGH(GPIOH_PIN12) | PIN_OSPEED_HIGH(GPIOH_PIN13) | PIN_OSPEED_HIGH(GPIOH_PIN14) | PIN_OSPEED_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | PIN_PUPDR_PULLUP(GPIOH_PIN2) | PIN_PUPDR_PULLUP(GPIOH_PIN3) | PIN_PUPDR_PULLUP(GPIOH_PIN4) | PIN_PUPDR_PULLUP(GPIOH_PIN5) | PIN_PUPDR_PULLUP(GPIOH_PIN6) | PIN_PUPDR_PULLUP(GPIOH_PIN7) | PIN_PUPDR_PULLUP(GPIOH_PIN8) | PIN_PUPDR_PULLUP(GPIOH_PIN9) | PIN_PUPDR_PULLUP(GPIOH_PIN10) | PIN_PUPDR_PULLUP(GPIOH_PIN11) | PIN_PUPDR_PULLUP(GPIOH_PIN12) | PIN_PUPDR_PULLUP(GPIOH_PIN13) | PIN_PUPDR_PULLUP(GPIOH_PIN14) | PIN_PUPDR_PULLUP(GPIOH_PIN15))
#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | PIN_ODR_HIGH(GPIOH_OSC_OUT) | PIN_ODR_HIGH(GPIOH_PIN2) | PIN_ODR_HIGH(GPIOH_PIN3) | PIN_ODR_HIGH(GPIOH_PIN4) | PIN_ODR_HIGH(GPIOH_PIN5) | PIN_ODR_HIGH(GPIOH_PIN6) | PIN_ODR_HIGH(GPIOH_PIN7) | PIN_ODR_HIGH(GPIOH_PIN8) | PIN_ODR_HIGH(GPIOH_PIN9) | PIN_ODR_HIGH(GPIOH_PIN10) | PIN_ODR_HIGH(GPIOH_PIN11) | PIN_ODR_HIGH(GPIOH_PIN12) | PIN_ODR_HIGH(GPIOH_PIN13) | PIN_ODR_HIGH(GPIOH_PIN14) | PIN_ODR_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | PIN_AFIO_AF(GPIOH_PIN2, 0U) | PIN_AFIO_AF(GPIOH_PIN3, 0U) | PIN_AFIO_AF(GPIOH_PIN4, 0U) | PIN_AFIO_AF(GPIOH_PIN5, 0U) | PIN_AFIO_AF(GPIOH_PIN6, 0U) | PIN_AFIO_AF(GPIOH_PIN7, 0U))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | PIN_AFIO_AF(GPIOH_PIN9, 0U) | PIN_AFIO_AF(GPIOH_PIN10, 0U) | PIN_AFIO_AF(GPIOH_PIN11, 0U) | PIN_AFIO_AF(GPIOH_PIN12, 0U) | PIN_AFIO_AF(GPIOH_PIN13, 0U) | PIN_AFIO_AF(GPIOH_PIN14, 0U) | PIN_AFIO_AF(GPIOH_PIN15, 0U))
/*
* GPIOI setup:
*
* PI0 - PIN0 (input pullup).
* PI1 - PIN1 (input pullup).
* PI2 - PIN2 (input pullup).
* PI3 - PIN3 (input pullup).
* PI4 - PIN4 (input pullup).
* PI5 - PIN5 (input pullup).
* PI6 - PIN6 (input pullup).
* PI7 - PIN7 (input pullup).
* PI8 - PIN8 (input pullup).
* PI9 - PIN9 (input pullup).
* PI10 - PIN10 (input pullup).
* PI11 - PIN11 (input pullup).
* PI12 - PIN12 (input pullup).
* PI13 - PIN13 (input pullup).
* PI14 - PIN14 (input pullup).
* PI15 - PIN15 (input pullup).
*/
#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | PIN_MODE_INPUT(GPIOI_PIN1) | PIN_MODE_INPUT(GPIOI_PIN2) | PIN_MODE_INPUT(GPIOI_PIN3) | PIN_MODE_INPUT(GPIOI_PIN4) | PIN_MODE_INPUT(GPIOI_PIN5) | PIN_MODE_INPUT(GPIOI_PIN6) | PIN_MODE_INPUT(GPIOI_PIN7) | PIN_MODE_INPUT(GPIOI_PIN8) | PIN_MODE_INPUT(GPIOI_PIN9) | PIN_MODE_INPUT(GPIOI_PIN10) | PIN_MODE_INPUT(GPIOI_PIN11) | PIN_MODE_INPUT(GPIOI_PIN12) | PIN_MODE_INPUT(GPIOI_PIN13) | PIN_MODE_INPUT(GPIOI_PIN14) | PIN_MODE_INPUT(GPIOI_PIN15))
#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | PIN_OSPEED_HIGH(GPIOI_PIN1) | PIN_OSPEED_HIGH(GPIOI_PIN2) | PIN_OSPEED_HIGH(GPIOI_PIN3) | PIN_OSPEED_HIGH(GPIOI_PIN4) | PIN_OSPEED_HIGH(GPIOI_PIN5) | PIN_OSPEED_HIGH(GPIOI_PIN6) | PIN_OSPEED_HIGH(GPIOI_PIN7) | PIN_OSPEED_HIGH(GPIOI_PIN8) | PIN_OSPEED_HIGH(GPIOI_PIN9) | PIN_OSPEED_HIGH(GPIOI_PIN10) | PIN_OSPEED_HIGH(GPIOI_PIN11) | PIN_OSPEED_HIGH(GPIOI_PIN12) | PIN_OSPEED_HIGH(GPIOI_PIN13) | PIN_OSPEED_HIGH(GPIOI_PIN14) | PIN_OSPEED_HIGH(GPIOI_PIN15))
#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | PIN_PUPDR_PULLUP(GPIOI_PIN1) | PIN_PUPDR_PULLUP(GPIOI_PIN2) | PIN_PUPDR_PULLUP(GPIOI_PIN3) | PIN_PUPDR_PULLUP(GPIOI_PIN4) | PIN_PUPDR_PULLUP(GPIOI_PIN5) | PIN_PUPDR_PULLUP(GPIOI_PIN6) | PIN_PUPDR_PULLUP(GPIOI_PIN7) | PIN_PUPDR_PULLUP(GPIOI_PIN8) | PIN_PUPDR_PULLUP(GPIOI_PIN9) | PIN_PUPDR_PULLUP(GPIOI_PIN10) | PIN_PUPDR_PULLUP(GPIOI_PIN11) | PIN_PUPDR_PULLUP(GPIOI_PIN12) | PIN_PUPDR_PULLUP(GPIOI_PIN13) | PIN_PUPDR_PULLUP(GPIOI_PIN14) | PIN_PUPDR_PULLUP(GPIOI_PIN15))
#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | PIN_ODR_HIGH(GPIOI_PIN1) | PIN_ODR_HIGH(GPIOI_PIN2) | PIN_ODR_HIGH(GPIOI_PIN3) | PIN_ODR_HIGH(GPIOI_PIN4) | PIN_ODR_HIGH(GPIOI_PIN5) | PIN_ODR_HIGH(GPIOI_PIN6) | PIN_ODR_HIGH(GPIOI_PIN7) | PIN_ODR_HIGH(GPIOI_PIN8) | PIN_ODR_HIGH(GPIOI_PIN9) | PIN_ODR_HIGH(GPIOI_PIN10) | PIN_ODR_HIGH(GPIOI_PIN11) | PIN_ODR_HIGH(GPIOI_PIN12) | PIN_ODR_HIGH(GPIOI_PIN13) | PIN_ODR_HIGH(GPIOI_PIN14) | PIN_ODR_HIGH(GPIOI_PIN15))
#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | PIN_AFIO_AF(GPIOI_PIN1, 0U) | PIN_AFIO_AF(GPIOI_PIN2, 0U) | PIN_AFIO_AF(GPIOI_PIN3, 0U) | PIN_AFIO_AF(GPIOI_PIN4, 0U) | PIN_AFIO_AF(GPIOI_PIN5, 0U) | PIN_AFIO_AF(GPIOI_PIN6, 0U) | PIN_AFIO_AF(GPIOI_PIN7, 0U))
#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | PIN_AFIO_AF(GPIOI_PIN9, 0U) | PIN_AFIO_AF(GPIOI_PIN10, 0U) | PIN_AFIO_AF(GPIOI_PIN11, 0U) | PIN_AFIO_AF(GPIOI_PIN12, 0U) | PIN_AFIO_AF(GPIOI_PIN13, 0U) | PIN_AFIO_AF(GPIOI_PIN14, 0U) | PIN_AFIO_AF(GPIOI_PIN15, 0U))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* BOARD_H */

1193
drivers/boards/BLACKPILL_STM32_F401/cfg/board.chcfg
View File

File diff suppressed because it is too large Load Diff

15
drivers/boards/BLACKPILL_STM32_F401/cfg/board.fmpp
Unescape View File

@ -1,15 +0,0 @@
sourceRoot: ../../../../../tools/ftl/processors/boards/stm32f4xx/templates
outputRoot: ..
dataRoot: .
freemarkerLinks: {
lib: ../../../../../tools/ftl/libs
}
data : {
doc1:xml (
board.chcfg
{
}
)
}

250
drivers/boards/BLACKPILL_STM32_F411/board.c
Unescape View File

@ -1,250 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#include "stm32_gpio.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief Type of STM32 GPIO port setup.
*/
typedef struct {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
/**
* @brief Type of STM32 GPIO initialization data.
*/
typedef struct {
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
gpio_setup_t PFData;
#endif
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
gpio_setup_t PGData;
#endif
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
gpio_setup_t PHData;
#endif
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
gpio_setup_t PIData;
#endif
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
gpio_setup_t PJData;
#endif
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
gpio_setup_t PKData;
#endif
} gpio_config_t;
/**
* @brief STM32 GPIO static initialization data.
*/
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
#endif
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB1(STM32_GPIO_EN_MASK);
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
#if STM32_HAS_GPIOF
gpio_init(GPIOF, &gpio_default_config.PFData);
#endif
#if STM32_HAS_GPIOG
gpio_init(GPIOG, &gpio_default_config.PGData);
#endif
#if STM32_HAS_GPIOH
gpio_init(GPIOH, &gpio_default_config.PHData);
#endif
#if STM32_HAS_GPIOI
gpio_init(GPIOI, &gpio_default_config.PIData);
#endif
#if STM32_HAS_GPIOJ
gpio_init(GPIOJ, &gpio_default_config.PJData);
#endif
#if STM32_HAS_GPIOK
gpio_init(GPIOK, &gpio_default_config.PKData);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {}
/**
* @brief Early initialization code.
* @details GPIO ports and system clocks are initialized before everything
* else.
*/
void __early_init(void) {
enter_bootloader_mode_if_requested();
stm32_gpio_init();
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {}

583
drivers/boards/BLACKPILL_STM32_F411/board.h
Unescape View File

@ -1,583 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* Setup for STM32F411CEU6 black pill board.
*/
/*
* Board identifier.
*/
#define BOARD_BLACKPILL_STM32_F411
#define BOARD_NAME "STM32F411CEU6 blackpill"
/*
* Allow Board to boot USB without extra A9 hardware/software config
*/
#define BOARD_OTG_NOVBUSSENS 1
/*
* Board oscillators-related settings.
*/
#if !defined(STM32_LSECLK)
# define STM32_LSECLK 32768U
#endif
#if !defined(STM32_HSECLK)
# define STM32_HSECLK 25000000U
#endif
//#define STM32_HSE_BYPASS
/*
* Board voltages.
* Required for performance limits calculation.
*/
#define STM32_VDD 300U
/*
* MCU type as defined in the ST header.
*/
#define STM32F411xE
/*
* IO pins assignments.
*/
#define GPIOA_ARD_A0 0U
#define GPIOA_ADC1_IN0 0U
#define GPIOA_ARD_A1 1U
#define GPIOA_ADC1_IN1 1U
#define GPIOA_ARD_D1 2U
#define GPIOA_USART2_TX 2U
#define GPIOA_ARD_D0 3U
#define GPIOA_USART2_RX 3U
#define GPIOA_ARD_A2 4U
#define GPIOA_ADC1_IN4 4U
#define GPIOA_LED_GREEN 5U
#define GPIOA_ARD_D13 5U
#define GPIOA_ARD_D12 6U
#define GPIOA_ARD_D11 7U
#define GPIOA_ARD_D7 8U
#define GPIOA_ARD_D8 9U
#define GPIOA_ARD_D2 10U
#define GPIOA_OTG_FS_DM 11U
#define GPIOA_OTG_FS_DP 12U
#define GPIOA_SWDIO 13U
#define GPIOA_SWCLK 14U
#define GPIOA_PIN15 15U
#define GPIOB_ARD_A3 0U
#define GPIOB_ADC1_IN8 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_SWO 3U
#define GPIOB_ARD_D3 3U
#define GPIOB_ARD_D5 4U
#define GPIOB_ARD_D4 5U
#define GPIOB_ARD_D10 6U
#define GPIOB_PIN7 7U
#define GPIOB_ARD_D15 8U
#define GPIOB_ARD_D14 9U
#define GPIOB_ARD_D6 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOC_ARD_A5 0U
#define GPIOC_ADC1_IN10 0U
#define GPIOC_ARD_A4 1U
#define GPIOC_ADC1_IN11 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN3 3U
#define GPIOC_PIN4 4U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_ARD_D9 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_BUTTON 13U
#define GPIOC_OSC32_IN 14U
#define GPIOC_OSC32_OUT 15U
#define GPIOD_PIN0 0U
#define GPIOD_PIN1 1U
#define GPIOD_PIN2 2U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_PIN12 12U
#define GPIOD_PIN13 13U
#define GPIOD_PIN14 14U
#define GPIOD_PIN15 15U
#define GPIOE_PIN0 0U
#define GPIOE_PIN1 1U
#define GPIOE_PIN2 2U
#define GPIOE_PIN3 3U
#define GPIOE_PIN4 4U
#define GPIOE_PIN5 5U
#define GPIOE_PIN6 6U
#define GPIOE_PIN7 7U
#define GPIOE_PIN8 8U
#define GPIOE_PIN9 9U
#define GPIOE_PIN10 10U
#define GPIOE_PIN11 11U
#define GPIOE_PIN12 12U
#define GPIOE_PIN13 13U
#define GPIOE_PIN14 14U
#define GPIOE_PIN15 15U
#define GPIOF_PIN0 0U
#define GPIOF_PIN1 1U
#define GPIOF_PIN2 2U
#define GPIOF_PIN3 3U
#define GPIOF_PIN4 4U
#define GPIOF_PIN5 5U
#define GPIOF_PIN6 6U
#define GPIOF_PIN7 7U
#define GPIOF_PIN8 8U
#define GPIOF_PIN9 9U
#define GPIOF_PIN10 10U
#define GPIOF_PIN11 11U
#define GPIOF_PIN12 12U
#define GPIOF_PIN13 13U
#define GPIOF_PIN14 14U
#define GPIOF_PIN15 15U
#define GPIOG_PIN0 0U
#define GPIOG_PIN1 1U
#define GPIOG_PIN2 2U
#define GPIOG_PIN3 3U
#define GPIOG_PIN4 4U
#define GPIOG_PIN5 5U
#define GPIOG_PIN6 6U
#define GPIOG_PIN7 7U
#define GPIOG_PIN8 8U
#define GPIOG_PIN9 9U
#define GPIOG_PIN10 10U
#define GPIOG_PIN11 11U
#define GPIOG_PIN12 12U
#define GPIOG_PIN13 13U
#define GPIOG_PIN14 14U
#define GPIOG_PIN15 15U
#define GPIOH_OSC_IN 0U
#define GPIOH_OSC_OUT 1U
#define GPIOH_PIN2 2U
#define GPIOH_PIN3 3U
#define GPIOH_PIN4 4U
#define GPIOH_PIN5 5U
#define GPIOH_PIN6 6U
#define GPIOH_PIN7 7U
#define GPIOH_PIN8 8U
#define GPIOH_PIN9 9U
#define GPIOH_PIN10 10U
#define GPIOH_PIN11 11U
#define GPIOH_PIN12 12U
#define GPIOH_PIN13 13U
#define GPIOH_PIN14 14U
#define GPIOH_PIN15 15U
#define GPIOI_PIN0 0U
#define GPIOI_PIN1 1U
#define GPIOI_PIN2 2U
#define GPIOI_PIN3 3U
#define GPIOI_PIN4 4U
#define GPIOI_PIN5 5U
#define GPIOI_PIN6 6U
#define GPIOI_PIN7 7U
#define GPIOI_PIN8 8U
#define GPIOI_PIN9 9U
#define GPIOI_PIN10 10U
#define GPIOI_PIN11 11U
#define GPIOI_PIN12 12U
#define GPIOI_PIN13 13U
#define GPIOI_PIN14 14U
#define GPIOI_PIN15 15U
/*
* IO lines assignments.
*/
#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U)
#define LINE_ADC1_IN0 PAL_LINE(GPIOA, 0U)
#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U)
#define LINE_ADC1_IN1 PAL_LINE(GPIOA, 1U)
#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U)
#define LINE_USART2_TX PAL_LINE(GPIOA, 2U)
#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U)
#define LINE_USART2_RX PAL_LINE(GPIOA, 3U)
#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U)
#define LINE_ADC1_IN4 PAL_LINE(GPIOA, 4U)
#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)
#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U)
#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U)
#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U)
#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U)
#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U)
#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U)
#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U)
#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U)
#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U)
#define LINE_ADC1_IN8 PAL_LINE(GPIOB, 0U)
#define LINE_SWO PAL_LINE(GPIOB, 3U)
#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U)
#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U)
#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U)
#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U)
#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)
#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U)
#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U)
#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U)
#define LINE_ADC1_IN10 PAL_LINE(GPIOC, 0U)
#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U)
#define LINE_ADC1_IN11 PAL_LINE(GPIOC, 1U)
#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U)
#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the STM32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)*2U))
#define PIN_MODE_OUTPUT(n) (1U << ((n)*2U))
#define PIN_MODE_ALTERNATE(n) (2U << ((n)*2U))
#define PIN_MODE_ANALOG(n) (3U << ((n)*2U))
#define PIN_ODR_LOW(n) (0U << (n))
#define PIN_ODR_HIGH(n) (1U << (n))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
#define PIN_OSPEED_VERYLOW(n) (0U << ((n)*2U))
#define PIN_OSPEED_LOW(n) (1U << ((n)*2U))
#define PIN_OSPEED_MEDIUM(n) (2U << ((n)*2U))
#define PIN_OSPEED_HIGH(n) (3U << ((n)*2U))
#define PIN_PUPDR_FLOATING(n) (0U << ((n)*2U))
#define PIN_PUPDR_PULLUP(n) (1U << ((n)*2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n)*2U))
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
/*
* GPIOA setup:
*
* PA0 - ARD_A0 ADC1_IN0 (input pullup).
* PA1 - ARD_A1 ADC1_IN1 (input pullup).
* PA2 - ARD_D1 USART2_TX (alternate 7).
* PA3 - ARD_D0 USART2_RX (alternate 7).
* PA4 - ARD_A2 ADC1_IN4 (input pullup).
* PA5 - LED_GREEN ARD_D13 (output pushpull high).
* PA6 - ARD_D12 (input pullup).
* PA7 - ARD_D11 (input pullup).
* PA8 - ARD_D7 (input pullup).
* PA9 - ARD_D8 (input pullup).
* PA10 - ARD_D2 (input pullup).
* PA11 - OTG_FS_DM (alternate 10).
* PA12 - OTG_FS_DP (alternate 10).
* PA13 - SWDIO (alternate 0).
* PA14 - SWCLK (alternate 0).
* PA15 - PIN15 (input pullup).
*/
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | PIN_MODE_INPUT(GPIOA_ARD_A1) | PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | PIN_MODE_INPUT(GPIOA_ARD_A2) | PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | PIN_MODE_INPUT(GPIOA_ARD_D12) | PIN_MODE_INPUT(GPIOA_ARD_D11) | PIN_MODE_INPUT(GPIOA_ARD_D7) | PIN_MODE_INPUT(GPIOA_ARD_D8) | PIN_MODE_INPUT(GPIOA_ARD_D2) | PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | PIN_MODE_ALTERNATE(GPIOA_SWDIO) | PIN_MODE_ALTERNATE(GPIOA_SWCLK) | PIN_MODE_INPUT(GPIOA_PIN15))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | PIN_OSPEED_HIGH(GPIOA_ARD_A1) | PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | PIN_OSPEED_HIGH(GPIOA_ARD_A2) | PIN_OSPEED_MEDIUM(GPIOA_LED_GREEN) | PIN_OSPEED_HIGH(GPIOA_ARD_D12) | PIN_OSPEED_HIGH(GPIOA_ARD_D11) | PIN_OSPEED_HIGH(GPIOA_ARD_D7) | PIN_OSPEED_HIGH(GPIOA_ARD_D8) | PIN_OSPEED_HIGH(GPIOA_ARD_D2) | PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | PIN_OSPEED_HIGH(GPIOA_SWDIO) | PIN_OSPEED_HIGH(GPIOA_SWCLK) | PIN_OSPEED_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | PIN_PUPDR_PULLUP(GPIOA_ARD_D7) | PIN_PUPDR_PULLUP(GPIOA_ARD_D8) | PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | PIN_PUPDR_PULLUP(GPIOA_SWDIO) | PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | PIN_PUPDR_PULLUP(GPIOA_PIN15))
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | PIN_ODR_HIGH(GPIOA_ARD_A1) | PIN_ODR_HIGH(GPIOA_ARD_D1) | PIN_ODR_HIGH(GPIOA_ARD_D0) | PIN_ODR_HIGH(GPIOA_ARD_A2) | PIN_ODR_LOW(GPIOA_LED_GREEN) | PIN_ODR_HIGH(GPIOA_ARD_D12) | PIN_ODR_HIGH(GPIOA_ARD_D11) | PIN_ODR_HIGH(GPIOA_ARD_D7) | PIN_ODR_HIGH(GPIOA_ARD_D8) | PIN_ODR_HIGH(GPIOA_ARD_D2) | PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | PIN_ODR_HIGH(GPIOA_SWDIO) | PIN_ODR_HIGH(GPIOA_SWCLK) | PIN_ODR_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | PIN_AFIO_AF(GPIOA_LED_GREEN, 0U) | PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | PIN_AFIO_AF(GPIOA_SWDIO, 0U) | PIN_AFIO_AF(GPIOA_SWCLK, 0U) | PIN_AFIO_AF(GPIOA_PIN15, 0U))
/*
* GPIOB setup:
*
* PB0 - ARD_A3 ADC1_IN8 (input pullup).
* PB1 - PIN1 (input pullup).
* PB2 - PIN2 (input pullup).
* PB3 - SWO ARD_D3 (alternate 0).
* PB4 - ARD_D5 (input pullup).
* PB5 - ARD_D4 (input pullup).
* PB6 - ARD_D10 (input pullup).
* PB7 - PIN7 (input pullup).
* PB8 - ARD_D15 (input pullup).
* PB9 - ARD_D14 (input pullup).
* PB10 - ARD_D6 (input pullup).
* PB11 - PIN11 (input pullup).
* PB12 - PIN12 (input pullup).
* PB13 - PIN13 (input pullup).
* PB14 - PIN14 (input pullup).
* PB15 - PIN15 (input pullup).
*/
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_ARD_A3) | PIN_MODE_INPUT(GPIOB_PIN1) | PIN_MODE_INPUT(GPIOB_PIN2) | PIN_MODE_ALTERNATE(GPIOB_SWO) | PIN_MODE_INPUT(GPIOB_ARD_D5) | PIN_MODE_INPUT(GPIOB_ARD_D4) | PIN_MODE_INPUT(GPIOB_ARD_D10) | PIN_MODE_INPUT(GPIOB_PIN7) | PIN_MODE_INPUT(GPIOB_ARD_D15) | PIN_MODE_INPUT(GPIOB_ARD_D14) | PIN_MODE_INPUT(GPIOB_ARD_D6) | PIN_MODE_INPUT(GPIOB_PIN11) | PIN_MODE_INPUT(GPIOB_PIN12) | PIN_MODE_INPUT(GPIOB_PIN13) | PIN_MODE_INPUT(GPIOB_PIN14) | PIN_MODE_INPUT(GPIOB_PIN15))
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | PIN_OTYPE_PUSHPULL(GPIOB_SWO) | PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | PIN_OSPEED_HIGH(GPIOB_PIN1) | PIN_OSPEED_HIGH(GPIOB_PIN2) | PIN_OSPEED_HIGH(GPIOB_SWO) | PIN_OSPEED_HIGH(GPIOB_ARD_D5) | PIN_OSPEED_HIGH(GPIOB_ARD_D4) | PIN_OSPEED_HIGH(GPIOB_ARD_D10) | PIN_OSPEED_HIGH(GPIOB_PIN7) | PIN_OSPEED_HIGH(GPIOB_ARD_D15) | PIN_OSPEED_HIGH(GPIOB_ARD_D14) | PIN_OSPEED_HIGH(GPIOB_ARD_D6) | PIN_OSPEED_HIGH(GPIOB_PIN11) | PIN_OSPEED_HIGH(GPIOB_PIN12) | PIN_OSPEED_HIGH(GPIOB_PIN13) | PIN_OSPEED_HIGH(GPIOB_PIN14) | PIN_OSPEED_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_A3) | PIN_PUPDR_PULLUP(GPIOB_PIN1) | PIN_PUPDR_PULLUP(GPIOB_PIN2) | PIN_PUPDR_PULLUP(GPIOB_SWO) | PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | PIN_PUPDR_PULLUP(GPIOB_ARD_D10) | PIN_PUPDR_PULLUP(GPIOB_PIN7) | PIN_PUPDR_PULLUP(GPIOB_ARD_D15) | PIN_PUPDR_PULLUP(GPIOB_ARD_D14) | PIN_PUPDR_PULLUP(GPIOB_ARD_D6) | PIN_PUPDR_PULLUP(GPIOB_PIN11) | PIN_PUPDR_PULLUP(GPIOB_PIN12) | PIN_PUPDR_PULLUP(GPIOB_PIN13) | PIN_PUPDR_PULLUP(GPIOB_PIN14) | PIN_PUPDR_PULLUP(GPIOB_PIN15))
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | PIN_ODR_HIGH(GPIOB_PIN1) | PIN_ODR_HIGH(GPIOB_PIN2) | PIN_ODR_HIGH(GPIOB_SWO) | PIN_ODR_HIGH(GPIOB_ARD_D5) | PIN_ODR_HIGH(GPIOB_ARD_D4) | PIN_ODR_HIGH(GPIOB_ARD_D10) | PIN_ODR_HIGH(GPIOB_PIN7) | PIN_ODR_HIGH(GPIOB_ARD_D15) | PIN_ODR_HIGH(GPIOB_ARD_D14) | PIN_ODR_HIGH(GPIOB_ARD_D6) | PIN_ODR_HIGH(GPIOB_PIN11) | PIN_ODR_HIGH(GPIOB_PIN12) | PIN_ODR_HIGH(GPIOB_PIN13) | PIN_ODR_HIGH(GPIOB_PIN14) | PIN_ODR_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | PIN_AFIO_AF(GPIOB_PIN1, 0U) | PIN_AFIO_AF(GPIOB_PIN2, 0U) | PIN_AFIO_AF(GPIOB_SWO, 0U) | PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | PIN_AFIO_AF(GPIOB_PIN7, 0U))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | PIN_AFIO_AF(GPIOB_PIN11, 0U) | PIN_AFIO_AF(GPIOB_PIN12, 0U) | PIN_AFIO_AF(GPIOB_PIN13, 0U) | PIN_AFIO_AF(GPIOB_PIN14, 0U) | PIN_AFIO_AF(GPIOB_PIN15, 0U))
/*
* GPIOC setup:
*
* PC0 - ARD_A5 ADC1_IN10 (input pullup).
* PC1 - ARD_A4 ADC1_IN11 (input pullup).
* PC2 - PIN2 (input pullup).
* PC3 - PIN3 (input pullup).
* PC4 - PIN4 (input pullup).
* PC5 - PIN5 (input pullup).
* PC6 - PIN6 (input pullup).
* PC7 - ARD_D9 (input pullup).
* PC8 - PIN8 (input pullup).
* PC9 - PIN9 (input pullup).
* PC10 - PIN10 (input pullup).
* PC11 - PIN11 (input pullup).
* PC12 - PIN12 (input pullup).
* PC13 - BUTTON (input floating).
* PC14 - OSC32_IN (input floating).
* PC15 - OSC32_OUT (input floating).
*/
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A5) | PIN_MODE_INPUT(GPIOC_ARD_A4) | PIN_MODE_INPUT(GPIOC_PIN2) | PIN_MODE_INPUT(GPIOC_PIN3) | PIN_MODE_INPUT(GPIOC_PIN4) | PIN_MODE_INPUT(GPIOC_PIN5) | PIN_MODE_INPUT(GPIOC_PIN6) | PIN_MODE_INPUT(GPIOC_ARD_D9) | PIN_MODE_INPUT(GPIOC_PIN8) | PIN_MODE_INPUT(GPIOC_PIN9) | PIN_MODE_INPUT(GPIOC_PIN10) | PIN_MODE_INPUT(GPIOC_PIN11) | PIN_MODE_INPUT(GPIOC_PIN12) | PIN_MODE_INPUT(GPIOC_BUTTON) | PIN_MODE_INPUT(GPIOC_OSC32_IN) | PIN_MODE_INPUT(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | PIN_OSPEED_HIGH(GPIOC_ARD_A4) | PIN_OSPEED_HIGH(GPIOC_PIN2) | PIN_OSPEED_HIGH(GPIOC_PIN3) | PIN_OSPEED_HIGH(GPIOC_PIN4) | PIN_OSPEED_HIGH(GPIOC_PIN5) | PIN_OSPEED_HIGH(GPIOC_PIN6) | PIN_OSPEED_HIGH(GPIOC_ARD_D9) | PIN_OSPEED_HIGH(GPIOC_PIN8) | PIN_OSPEED_HIGH(GPIOC_PIN9) | PIN_OSPEED_HIGH(GPIOC_PIN10) | PIN_OSPEED_HIGH(GPIOC_PIN11) | PIN_OSPEED_HIGH(GPIOC_PIN12) | PIN_OSPEED_HIGH(GPIOC_BUTTON) | PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A5) | PIN_PUPDR_PULLUP(GPIOC_ARD_A4) | PIN_PUPDR_PULLUP(GPIOC_PIN2) | PIN_PUPDR_PULLUP(GPIOC_PIN3) | PIN_PUPDR_PULLUP(GPIOC_PIN4) | PIN_PUPDR_PULLUP(GPIOC_PIN5) | PIN_PUPDR_PULLUP(GPIOC_PIN6) | PIN_PUPDR_PULLUP(GPIOC_ARD_D9) | PIN_PUPDR_PULLUP(GPIOC_PIN8) | PIN_PUPDR_PULLUP(GPIOC_PIN9) | PIN_PUPDR_PULLUP(GPIOC_PIN10) | PIN_PUPDR_PULLUP(GPIOC_PIN11) | PIN_PUPDR_PULLUP(GPIOC_PIN12) | PIN_PUPDR_FLOATING(GPIOC_BUTTON) | PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | PIN_ODR_HIGH(GPIOC_ARD_A4) | PIN_ODR_HIGH(GPIOC_PIN2) | PIN_ODR_HIGH(GPIOC_PIN3) | PIN_ODR_HIGH(GPIOC_PIN4) | PIN_ODR_HIGH(GPIOC_PIN5) | PIN_ODR_HIGH(GPIOC_PIN6) | PIN_ODR_HIGH(GPIOC_ARD_D9) | PIN_ODR_HIGH(GPIOC_PIN8) | PIN_ODR_HIGH(GPIOC_PIN9) | PIN_ODR_HIGH(GPIOC_PIN10) | PIN_ODR_HIGH(GPIOC_PIN11) | PIN_ODR_HIGH(GPIOC_PIN12) | PIN_ODR_HIGH(GPIOC_BUTTON) | PIN_ODR_HIGH(GPIOC_OSC32_IN) | PIN_ODR_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | PIN_AFIO_AF(GPIOC_PIN2, 0U) | PIN_AFIO_AF(GPIOC_PIN3, 0U) | PIN_AFIO_AF(GPIOC_PIN4, 0U) | PIN_AFIO_AF(GPIOC_PIN5, 0U) | PIN_AFIO_AF(GPIOC_PIN6, 0U) | PIN_AFIO_AF(GPIOC_ARD_D9, 0U))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | PIN_AFIO_AF(GPIOC_PIN9, 0U) | PIN_AFIO_AF(GPIOC_PIN10, 0U) | PIN_AFIO_AF(GPIOC_PIN11, 0U) | PIN_AFIO_AF(GPIOC_PIN12, 0U) | PIN_AFIO_AF(GPIOC_BUTTON, 0U) | PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
/*
* GPIOD setup:
*
* PD0 - PIN0 (input pullup).
* PD1 - PIN1 (input pullup).
* PD2 - PIN2 (input pullup).
* PD3 - PIN3 (input pullup).
* PD4 - PIN4 (input pullup).
* PD5 - PIN5 (input pullup).
* PD6 - PIN6 (input pullup).
* PD7 - PIN7 (input pullup).
* PD8 - PIN8 (input pullup).
* PD9 - PIN9 (input pullup).
* PD10 - PIN10 (input pullup).
* PD11 - PIN11 (input pullup).
* PD12 - PIN12 (input pullup).
* PD13 - PIN13 (input pullup).
* PD14 - PIN14 (input pullup).
* PD15 - PIN15 (input pullup).
*/
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | PIN_MODE_INPUT(GPIOD_PIN1) | PIN_MODE_INPUT(GPIOD_PIN2) | PIN_MODE_INPUT(GPIOD_PIN3) | PIN_MODE_INPUT(GPIOD_PIN4) | PIN_MODE_INPUT(GPIOD_PIN5) | PIN_MODE_INPUT(GPIOD_PIN6) | PIN_MODE_INPUT(GPIOD_PIN7) | PIN_MODE_INPUT(GPIOD_PIN8) | PIN_MODE_INPUT(GPIOD_PIN9) | PIN_MODE_INPUT(GPIOD_PIN10) | PIN_MODE_INPUT(GPIOD_PIN11) | PIN_MODE_INPUT(GPIOD_PIN12) | PIN_MODE_INPUT(GPIOD_PIN13) | PIN_MODE_INPUT(GPIOD_PIN14) | PIN_MODE_INPUT(GPIOD_PIN15))
#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | PIN_OSPEED_HIGH(GPIOD_PIN1) | PIN_OSPEED_HIGH(GPIOD_PIN2) | PIN_OSPEED_HIGH(GPIOD_PIN3) | PIN_OSPEED_HIGH(GPIOD_PIN4) | PIN_OSPEED_HIGH(GPIOD_PIN5) | PIN_OSPEED_HIGH(GPIOD_PIN6) | PIN_OSPEED_HIGH(GPIOD_PIN7) | PIN_OSPEED_HIGH(GPIOD_PIN8) | PIN_OSPEED_HIGH(GPIOD_PIN9) | PIN_OSPEED_HIGH(GPIOD_PIN10) | PIN_OSPEED_HIGH(GPIOD_PIN11) | PIN_OSPEED_HIGH(GPIOD_PIN12) | PIN_OSPEED_HIGH(GPIOD_PIN13) | PIN_OSPEED_HIGH(GPIOD_PIN14) | PIN_OSPEED_HIGH(GPIOD_PIN15))
#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | PIN_PUPDR_PULLUP(GPIOD_PIN1) | PIN_PUPDR_PULLUP(GPIOD_PIN2) | PIN_PUPDR_PULLUP(GPIOD_PIN3) | PIN_PUPDR_PULLUP(GPIOD_PIN4) | PIN_PUPDR_PULLUP(GPIOD_PIN5) | PIN_PUPDR_PULLUP(GPIOD_PIN6) | PIN_PUPDR_PULLUP(GPIOD_PIN7) | PIN_PUPDR_PULLUP(GPIOD_PIN8) | PIN_PUPDR_PULLUP(GPIOD_PIN9) | PIN_PUPDR_PULLUP(GPIOD_PIN10) | PIN_PUPDR_PULLUP(GPIOD_PIN11) | PIN_PUPDR_PULLUP(GPIOD_PIN12) | PIN_PUPDR_PULLUP(GPIOD_PIN13) | PIN_PUPDR_PULLUP(GPIOD_PIN14) | PIN_PUPDR_PULLUP(GPIOD_PIN15))
#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | PIN_ODR_HIGH(GPIOD_PIN1) | PIN_ODR_HIGH(GPIOD_PIN2) | PIN_ODR_HIGH(GPIOD_PIN3) | PIN_ODR_HIGH(GPIOD_PIN4) | PIN_ODR_HIGH(GPIOD_PIN5) | PIN_ODR_HIGH(GPIOD_PIN6) | PIN_ODR_HIGH(GPIOD_PIN7) | PIN_ODR_HIGH(GPIOD_PIN8) | PIN_ODR_HIGH(GPIOD_PIN9) | PIN_ODR_HIGH(GPIOD_PIN10) | PIN_ODR_HIGH(GPIOD_PIN11) | PIN_ODR_HIGH(GPIOD_PIN12) | PIN_ODR_HIGH(GPIOD_PIN13) | PIN_ODR_HIGH(GPIOD_PIN14) | PIN_ODR_HIGH(GPIOD_PIN15))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | PIN_AFIO_AF(GPIOD_PIN1, 0U) | PIN_AFIO_AF(GPIOD_PIN2, 0U) | PIN_AFIO_AF(GPIOD_PIN3, 0U) | PIN_AFIO_AF(GPIOD_PIN4, 0U) | PIN_AFIO_AF(GPIOD_PIN5, 0U) | PIN_AFIO_AF(GPIOD_PIN6, 0U) | PIN_AFIO_AF(GPIOD_PIN7, 0U))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | PIN_AFIO_AF(GPIOD_PIN9, 0U) | PIN_AFIO_AF(GPIOD_PIN10, 0U) | PIN_AFIO_AF(GPIOD_PIN11, 0U) | PIN_AFIO_AF(GPIOD_PIN12, 0U) | PIN_AFIO_AF(GPIOD_PIN13, 0U) | PIN_AFIO_AF(GPIOD_PIN14, 0U) | PIN_AFIO_AF(GPIOD_PIN15, 0U))
/*
* GPIOE setup:
*
* PE0 - PIN0 (input pullup).
* PE1 - PIN1 (input pullup).
* PE2 - PIN2 (input pullup).
* PE3 - PIN3 (input pullup).
* PE4 - PIN4 (input pullup).
* PE5 - PIN5 (input pullup).
* PE6 - PIN6 (input pullup).
* PE7 - PIN7 (input pullup).
* PE8 - PIN8 (input pullup).
* PE9 - PIN9 (input pullup).
* PE10 - PIN10 (input pullup).
* PE11 - PIN11 (input pullup).
* PE12 - PIN12 (input pullup).
* PE13 - PIN13 (input pullup).
* PE14 - PIN14 (input pullup).
* PE15 - PIN15 (input pullup).
*/
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | PIN_MODE_INPUT(GPIOE_PIN1) | PIN_MODE_INPUT(GPIOE_PIN2) | PIN_MODE_INPUT(GPIOE_PIN3) | PIN_MODE_INPUT(GPIOE_PIN4) | PIN_MODE_INPUT(GPIOE_PIN5) | PIN_MODE_INPUT(GPIOE_PIN6) | PIN_MODE_INPUT(GPIOE_PIN7) | PIN_MODE_INPUT(GPIOE_PIN8) | PIN_MODE_INPUT(GPIOE_PIN9) | PIN_MODE_INPUT(GPIOE_PIN10) | PIN_MODE_INPUT(GPIOE_PIN11) | PIN_MODE_INPUT(GPIOE_PIN12) | PIN_MODE_INPUT(GPIOE_PIN13) | PIN_MODE_INPUT(GPIOE_PIN14) | PIN_MODE_INPUT(GPIOE_PIN15))
#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | PIN_OSPEED_HIGH(GPIOE_PIN1) | PIN_OSPEED_HIGH(GPIOE_PIN2) | PIN_OSPEED_HIGH(GPIOE_PIN3) | PIN_OSPEED_HIGH(GPIOE_PIN4) | PIN_OSPEED_HIGH(GPIOE_PIN5) | PIN_OSPEED_HIGH(GPIOE_PIN6) | PIN_OSPEED_HIGH(GPIOE_PIN7) | PIN_OSPEED_HIGH(GPIOE_PIN8) | PIN_OSPEED_HIGH(GPIOE_PIN9) | PIN_OSPEED_HIGH(GPIOE_PIN10) | PIN_OSPEED_HIGH(GPIOE_PIN11) | PIN_OSPEED_HIGH(GPIOE_PIN12) | PIN_OSPEED_HIGH(GPIOE_PIN13) | PIN_OSPEED_HIGH(GPIOE_PIN14) | PIN_OSPEED_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | PIN_PUPDR_PULLUP(GPIOE_PIN1) | PIN_PUPDR_PULLUP(GPIOE_PIN2) | PIN_PUPDR_PULLUP(GPIOE_PIN3) | PIN_PUPDR_PULLUP(GPIOE_PIN4) | PIN_PUPDR_PULLUP(GPIOE_PIN5) | PIN_PUPDR_PULLUP(GPIOE_PIN6) | PIN_PUPDR_PULLUP(GPIOE_PIN7) | PIN_PUPDR_PULLUP(GPIOE_PIN8) | PIN_PUPDR_PULLUP(GPIOE_PIN9) | PIN_PUPDR_PULLUP(GPIOE_PIN10) | PIN_PUPDR_PULLUP(GPIOE_PIN11) | PIN_PUPDR_PULLUP(GPIOE_PIN12) | PIN_PUPDR_PULLUP(GPIOE_PIN13) | PIN_PUPDR_PULLUP(GPIOE_PIN14) | PIN_PUPDR_PULLUP(GPIOE_PIN15))
#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | PIN_ODR_HIGH(GPIOE_PIN1) | PIN_ODR_HIGH(GPIOE_PIN2) | PIN_ODR_HIGH(GPIOE_PIN3) | PIN_ODR_HIGH(GPIOE_PIN4) | PIN_ODR_HIGH(GPIOE_PIN5) | PIN_ODR_HIGH(GPIOE_PIN6) | PIN_ODR_HIGH(GPIOE_PIN7) | PIN_ODR_HIGH(GPIOE_PIN8) | PIN_ODR_HIGH(GPIOE_PIN9) | PIN_ODR_HIGH(GPIOE_PIN10) | PIN_ODR_HIGH(GPIOE_PIN11) | PIN_ODR_HIGH(GPIOE_PIN12) | PIN_ODR_HIGH(GPIOE_PIN13) | PIN_ODR_HIGH(GPIOE_PIN14) | PIN_ODR_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | PIN_AFIO_AF(GPIOE_PIN1, 0U) | PIN_AFIO_AF(GPIOE_PIN2, 0U) | PIN_AFIO_AF(GPIOE_PIN3, 0U) | PIN_AFIO_AF(GPIOE_PIN4, 0U) | PIN_AFIO_AF(GPIOE_PIN5, 0U) | PIN_AFIO_AF(GPIOE_PIN6, 0U) | PIN_AFIO_AF(GPIOE_PIN7, 0U))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | PIN_AFIO_AF(GPIOE_PIN9, 0U) | PIN_AFIO_AF(GPIOE_PIN10, 0U) | PIN_AFIO_AF(GPIOE_PIN11, 0U) | PIN_AFIO_AF(GPIOE_PIN12, 0U) | PIN_AFIO_AF(GPIOE_PIN13, 0U) | PIN_AFIO_AF(GPIOE_PIN14, 0U) | PIN_AFIO_AF(GPIOE_PIN15, 0U))
/*
* GPIOF setup:
*
* PF0 - PIN0 (input pullup).
* PF1 - PIN1 (input pullup).
* PF2 - PIN2 (input pullup).
* PF3 - PIN3 (input pullup).
* PF4 - PIN4 (input pullup).
* PF5 - PIN5 (input pullup).
* PF6 - PIN6 (input pullup).
* PF7 - PIN7 (input pullup).
* PF8 - PIN8 (input pullup).
* PF9 - PIN9 (input pullup).
* PF10 - PIN10 (input pullup).
* PF11 - PIN11 (input pullup).
* PF12 - PIN12 (input pullup).
* PF13 - PIN13 (input pullup).
* PF14 - PIN14 (input pullup).
* PF15 - PIN15 (input pullup).
*/
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | PIN_MODE_INPUT(GPIOF_PIN1) | PIN_MODE_INPUT(GPIOF_PIN2) | PIN_MODE_INPUT(GPIOF_PIN3) | PIN_MODE_INPUT(GPIOF_PIN4) | PIN_MODE_INPUT(GPIOF_PIN5) | PIN_MODE_INPUT(GPIOF_PIN6) | PIN_MODE_INPUT(GPIOF_PIN7) | PIN_MODE_INPUT(GPIOF_PIN8) | PIN_MODE_INPUT(GPIOF_PIN9) | PIN_MODE_INPUT(GPIOF_PIN10) | PIN_MODE_INPUT(GPIOF_PIN11) | PIN_MODE_INPUT(GPIOF_PIN12) | PIN_MODE_INPUT(GPIOF_PIN13) | PIN_MODE_INPUT(GPIOF_PIN14) | PIN_MODE_INPUT(GPIOF_PIN15))
#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | PIN_OSPEED_HIGH(GPIOF_PIN1) | PIN_OSPEED_HIGH(GPIOF_PIN2) | PIN_OSPEED_HIGH(GPIOF_PIN3) | PIN_OSPEED_HIGH(GPIOF_PIN4) | PIN_OSPEED_HIGH(GPIOF_PIN5) | PIN_OSPEED_HIGH(GPIOF_PIN6) | PIN_OSPEED_HIGH(GPIOF_PIN7) | PIN_OSPEED_HIGH(GPIOF_PIN8) | PIN_OSPEED_HIGH(GPIOF_PIN9) | PIN_OSPEED_HIGH(GPIOF_PIN10) | PIN_OSPEED_HIGH(GPIOF_PIN11) | PIN_OSPEED_HIGH(GPIOF_PIN12) | PIN_OSPEED_HIGH(GPIOF_PIN13) | PIN_OSPEED_HIGH(GPIOF_PIN14) | PIN_OSPEED_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | PIN_PUPDR_PULLUP(GPIOF_PIN1) | PIN_PUPDR_PULLUP(GPIOF_PIN2) | PIN_PUPDR_PULLUP(GPIOF_PIN3) | PIN_PUPDR_PULLUP(GPIOF_PIN4) | PIN_PUPDR_PULLUP(GPIOF_PIN5) | PIN_PUPDR_PULLUP(GPIOF_PIN6) | PIN_PUPDR_PULLUP(GPIOF_PIN7) | PIN_PUPDR_PULLUP(GPIOF_PIN8) | PIN_PUPDR_PULLUP(GPIOF_PIN9) | PIN_PUPDR_PULLUP(GPIOF_PIN10) | PIN_PUPDR_PULLUP(GPIOF_PIN11) | PIN_PUPDR_PULLUP(GPIOF_PIN12) | PIN_PUPDR_PULLUP(GPIOF_PIN13) | PIN_PUPDR_PULLUP(GPIOF_PIN14) | PIN_PUPDR_PULLUP(GPIOF_PIN15))
#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | PIN_ODR_HIGH(GPIOF_PIN1) | PIN_ODR_HIGH(GPIOF_PIN2) | PIN_ODR_HIGH(GPIOF_PIN3) | PIN_ODR_HIGH(GPIOF_PIN4) | PIN_ODR_HIGH(GPIOF_PIN5) | PIN_ODR_HIGH(GPIOF_PIN6) | PIN_ODR_HIGH(GPIOF_PIN7) | PIN_ODR_HIGH(GPIOF_PIN8) | PIN_ODR_HIGH(GPIOF_PIN9) | PIN_ODR_HIGH(GPIOF_PIN10) | PIN_ODR_HIGH(GPIOF_PIN11) | PIN_ODR_HIGH(GPIOF_PIN12) | PIN_ODR_HIGH(GPIOF_PIN13) | PIN_ODR_HIGH(GPIOF_PIN14) | PIN_ODR_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | PIN_AFIO_AF(GPIOF_PIN1, 0U) | PIN_AFIO_AF(GPIOF_PIN2, 0U) | PIN_AFIO_AF(GPIOF_PIN3, 0U) | PIN_AFIO_AF(GPIOF_PIN4, 0U) | PIN_AFIO_AF(GPIOF_PIN5, 0U) | PIN_AFIO_AF(GPIOF_PIN6, 0U) | PIN_AFIO_AF(GPIOF_PIN7, 0U))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | PIN_AFIO_AF(GPIOF_PIN9, 0U) | PIN_AFIO_AF(GPIOF_PIN10, 0U) | PIN_AFIO_AF(GPIOF_PIN11, 0U) | PIN_AFIO_AF(GPIOF_PIN12, 0U) | PIN_AFIO_AF(GPIOF_PIN13, 0U) | PIN_AFIO_AF(GPIOF_PIN14, 0U) | PIN_AFIO_AF(GPIOF_PIN15, 0U))
/*
* GPIOG setup:
*
* PG0 - PIN0 (input pullup).
* PG1 - PIN1 (input pullup).
* PG2 - PIN2 (input pullup).
* PG3 - PIN3 (input pullup).
* PG4 - PIN4 (input pullup).
* PG5 - PIN5 (input pullup).
* PG6 - PIN6 (input pullup).
* PG7 - PIN7 (input pullup).
* PG8 - PIN8 (input pullup).
* PG9 - PIN9 (input pullup).
* PG10 - PIN10 (input pullup).
* PG11 - PIN11 (input pullup).
* PG12 - PIN12 (input pullup).
* PG13 - PIN13 (input pullup).
* PG14 - PIN14 (input pullup).
* PG15 - PIN15 (input pullup).
*/
#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | PIN_MODE_INPUT(GPIOG_PIN1) | PIN_MODE_INPUT(GPIOG_PIN2) | PIN_MODE_INPUT(GPIOG_PIN3) | PIN_MODE_INPUT(GPIOG_PIN4) | PIN_MODE_INPUT(GPIOG_PIN5) | PIN_MODE_INPUT(GPIOG_PIN6) | PIN_MODE_INPUT(GPIOG_PIN7) | PIN_MODE_INPUT(GPIOG_PIN8) | PIN_MODE_INPUT(GPIOG_PIN9) | PIN_MODE_INPUT(GPIOG_PIN10) | PIN_MODE_INPUT(GPIOG_PIN11) | PIN_MODE_INPUT(GPIOG_PIN12) | PIN_MODE_INPUT(GPIOG_PIN13) | PIN_MODE_INPUT(GPIOG_PIN14) | PIN_MODE_INPUT(GPIOG_PIN15))
#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | PIN_OSPEED_HIGH(GPIOG_PIN1) | PIN_OSPEED_HIGH(GPIOG_PIN2) | PIN_OSPEED_HIGH(GPIOG_PIN3) | PIN_OSPEED_HIGH(GPIOG_PIN4) | PIN_OSPEED_HIGH(GPIOG_PIN5) | PIN_OSPEED_HIGH(GPIOG_PIN6) | PIN_OSPEED_HIGH(GPIOG_PIN7) | PIN_OSPEED_HIGH(GPIOG_PIN8) | PIN_OSPEED_HIGH(GPIOG_PIN9) | PIN_OSPEED_HIGH(GPIOG_PIN10) | PIN_OSPEED_HIGH(GPIOG_PIN11) | PIN_OSPEED_HIGH(GPIOG_PIN12) | PIN_OSPEED_HIGH(GPIOG_PIN13) | PIN_OSPEED_HIGH(GPIOG_PIN14) | PIN_OSPEED_HIGH(GPIOG_PIN15))
#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | PIN_PUPDR_PULLUP(GPIOG_PIN1) | PIN_PUPDR_PULLUP(GPIOG_PIN2) | PIN_PUPDR_PULLUP(GPIOG_PIN3) | PIN_PUPDR_PULLUP(GPIOG_PIN4) | PIN_PUPDR_PULLUP(GPIOG_PIN5) | PIN_PUPDR_PULLUP(GPIOG_PIN6) | PIN_PUPDR_PULLUP(GPIOG_PIN7) | PIN_PUPDR_PULLUP(GPIOG_PIN8) | PIN_PUPDR_PULLUP(GPIOG_PIN9) | PIN_PUPDR_PULLUP(GPIOG_PIN10) | PIN_PUPDR_PULLUP(GPIOG_PIN11) | PIN_PUPDR_PULLUP(GPIOG_PIN12) | PIN_PUPDR_PULLUP(GPIOG_PIN13) | PIN_PUPDR_PULLUP(GPIOG_PIN14) | PIN_PUPDR_PULLUP(GPIOG_PIN15))
#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | PIN_ODR_HIGH(GPIOG_PIN1) | PIN_ODR_HIGH(GPIOG_PIN2) | PIN_ODR_HIGH(GPIOG_PIN3) | PIN_ODR_HIGH(GPIOG_PIN4) | PIN_ODR_HIGH(GPIOG_PIN5) | PIN_ODR_HIGH(GPIOG_PIN6) | PIN_ODR_HIGH(GPIOG_PIN7) | PIN_ODR_HIGH(GPIOG_PIN8) | PIN_ODR_HIGH(GPIOG_PIN9) | PIN_ODR_HIGH(GPIOG_PIN10) | PIN_ODR_HIGH(GPIOG_PIN11) | PIN_ODR_HIGH(GPIOG_PIN12) | PIN_ODR_HIGH(GPIOG_PIN13) | PIN_ODR_HIGH(GPIOG_PIN14) | PIN_ODR_HIGH(GPIOG_PIN15))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | PIN_AFIO_AF(GPIOG_PIN1, 0U) | PIN_AFIO_AF(GPIOG_PIN2, 0U) | PIN_AFIO_AF(GPIOG_PIN3, 0U) | PIN_AFIO_AF(GPIOG_PIN4, 0U) | PIN_AFIO_AF(GPIOG_PIN5, 0U) | PIN_AFIO_AF(GPIOG_PIN6, 0U) | PIN_AFIO_AF(GPIOG_PIN7, 0U))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | PIN_AFIO_AF(GPIOG_PIN9, 0U) | PIN_AFIO_AF(GPIOG_PIN10, 0U) | PIN_AFIO_AF(GPIOG_PIN11, 0U) | PIN_AFIO_AF(GPIOG_PIN12, 0U) | PIN_AFIO_AF(GPIOG_PIN13, 0U) | PIN_AFIO_AF(GPIOG_PIN14, 0U) | PIN_AFIO_AF(GPIOG_PIN15, 0U))
/*
* GPIOH setup:
*
* PH0 - OSC_IN (input floating).
* PH1 - OSC_OUT (input floating).
* PH2 - PIN2 (input pullup).
* PH3 - PIN3 (input pullup).
* PH4 - PIN4 (input pullup).
* PH5 - PIN5 (input pullup).
* PH6 - PIN6 (input pullup).
* PH7 - PIN7 (input pullup).
* PH8 - PIN8 (input pullup).
* PH9 - PIN9 (input pullup).
* PH10 - PIN10 (input pullup).
* PH11 - PIN11 (input pullup).
* PH12 - PIN12 (input pullup).
* PH13 - PIN13 (input pullup).
* PH14 - PIN14 (input pullup).
* PH15 - PIN15 (input pullup).
*/
#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | PIN_MODE_INPUT(GPIOH_OSC_OUT) | PIN_MODE_INPUT(GPIOH_PIN2) | PIN_MODE_INPUT(GPIOH_PIN3) | PIN_MODE_INPUT(GPIOH_PIN4) | PIN_MODE_INPUT(GPIOH_PIN5) | PIN_MODE_INPUT(GPIOH_PIN6) | PIN_MODE_INPUT(GPIOH_PIN7) | PIN_MODE_INPUT(GPIOH_PIN8) | PIN_MODE_INPUT(GPIOH_PIN9) | PIN_MODE_INPUT(GPIOH_PIN10) | PIN_MODE_INPUT(GPIOH_PIN11) | PIN_MODE_INPUT(GPIOH_PIN12) | PIN_MODE_INPUT(GPIOH_PIN13) | PIN_MODE_INPUT(GPIOH_PIN14) | PIN_MODE_INPUT(GPIOH_PIN15))
#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | PIN_OSPEED_HIGH(GPIOH_PIN2) | PIN_OSPEED_HIGH(GPIOH_PIN3) | PIN_OSPEED_HIGH(GPIOH_PIN4) | PIN_OSPEED_HIGH(GPIOH_PIN5) | PIN_OSPEED_HIGH(GPIOH_PIN6) | PIN_OSPEED_HIGH(GPIOH_PIN7) | PIN_OSPEED_HIGH(GPIOH_PIN8) | PIN_OSPEED_HIGH(GPIOH_PIN9) | PIN_OSPEED_HIGH(GPIOH_PIN10) | PIN_OSPEED_HIGH(GPIOH_PIN11) | PIN_OSPEED_HIGH(GPIOH_PIN12) | PIN_OSPEED_HIGH(GPIOH_PIN13) | PIN_OSPEED_HIGH(GPIOH_PIN14) | PIN_OSPEED_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | PIN_PUPDR_PULLUP(GPIOH_PIN2) | PIN_PUPDR_PULLUP(GPIOH_PIN3) | PIN_PUPDR_PULLUP(GPIOH_PIN4) | PIN_PUPDR_PULLUP(GPIOH_PIN5) | PIN_PUPDR_PULLUP(GPIOH_PIN6) | PIN_PUPDR_PULLUP(GPIOH_PIN7) | PIN_PUPDR_PULLUP(GPIOH_PIN8) | PIN_PUPDR_PULLUP(GPIOH_PIN9) | PIN_PUPDR_PULLUP(GPIOH_PIN10) | PIN_PUPDR_PULLUP(GPIOH_PIN11) | PIN_PUPDR_PULLUP(GPIOH_PIN12) | PIN_PUPDR_PULLUP(GPIOH_PIN13) | PIN_PUPDR_PULLUP(GPIOH_PIN14) | PIN_PUPDR_PULLUP(GPIOH_PIN15))
#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | PIN_ODR_HIGH(GPIOH_OSC_OUT) | PIN_ODR_HIGH(GPIOH_PIN2) | PIN_ODR_HIGH(GPIOH_PIN3) | PIN_ODR_HIGH(GPIOH_PIN4) | PIN_ODR_HIGH(GPIOH_PIN5) | PIN_ODR_HIGH(GPIOH_PIN6) | PIN_ODR_HIGH(GPIOH_PIN7) | PIN_ODR_HIGH(GPIOH_PIN8) | PIN_ODR_HIGH(GPIOH_PIN9) | PIN_ODR_HIGH(GPIOH_PIN10) | PIN_ODR_HIGH(GPIOH_PIN11) | PIN_ODR_HIGH(GPIOH_PIN12) | PIN_ODR_HIGH(GPIOH_PIN13) | PIN_ODR_HIGH(GPIOH_PIN14) | PIN_ODR_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | PIN_AFIO_AF(GPIOH_PIN2, 0U) | PIN_AFIO_AF(GPIOH_PIN3, 0U) | PIN_AFIO_AF(GPIOH_PIN4, 0U) | PIN_AFIO_AF(GPIOH_PIN5, 0U) | PIN_AFIO_AF(GPIOH_PIN6, 0U) | PIN_AFIO_AF(GPIOH_PIN7, 0U))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | PIN_AFIO_AF(GPIOH_PIN9, 0U) | PIN_AFIO_AF(GPIOH_PIN10, 0U) | PIN_AFIO_AF(GPIOH_PIN11, 0U) | PIN_AFIO_AF(GPIOH_PIN12, 0U) | PIN_AFIO_AF(GPIOH_PIN13, 0U) | PIN_AFIO_AF(GPIOH_PIN14, 0U) | PIN_AFIO_AF(GPIOH_PIN15, 0U))
/*
* GPIOI setup:
*
* PI0 - PIN0 (input pullup).
* PI1 - PIN1 (input pullup).
* PI2 - PIN2 (input pullup).
* PI3 - PIN3 (input pullup).
* PI4 - PIN4 (input pullup).
* PI5 - PIN5 (input pullup).
* PI6 - PIN6 (input pullup).
* PI7 - PIN7 (input pullup).
* PI8 - PIN8 (input pullup).
* PI9 - PIN9 (input pullup).
* PI10 - PIN10 (input pullup).
* PI11 - PIN11 (input pullup).
* PI12 - PIN12 (input pullup).
* PI13 - PIN13 (input pullup).
* PI14 - PIN14 (input pullup).
* PI15 - PIN15 (input pullup).
*/
#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | PIN_MODE_INPUT(GPIOI_PIN1) | PIN_MODE_INPUT(GPIOI_PIN2) | PIN_MODE_INPUT(GPIOI_PIN3) | PIN_MODE_INPUT(GPIOI_PIN4) | PIN_MODE_INPUT(GPIOI_PIN5) | PIN_MODE_INPUT(GPIOI_PIN6) | PIN_MODE_INPUT(GPIOI_PIN7) | PIN_MODE_INPUT(GPIOI_PIN8) | PIN_MODE_INPUT(GPIOI_PIN9) | PIN_MODE_INPUT(GPIOI_PIN10) | PIN_MODE_INPUT(GPIOI_PIN11) | PIN_MODE_INPUT(GPIOI_PIN12) | PIN_MODE_INPUT(GPIOI_PIN13) | PIN_MODE_INPUT(GPIOI_PIN14) | PIN_MODE_INPUT(GPIOI_PIN15))
#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | PIN_OSPEED_HIGH(GPIOI_PIN1) | PIN_OSPEED_HIGH(GPIOI_PIN2) | PIN_OSPEED_HIGH(GPIOI_PIN3) | PIN_OSPEED_HIGH(GPIOI_PIN4) | PIN_OSPEED_HIGH(GPIOI_PIN5) | PIN_OSPEED_HIGH(GPIOI_PIN6) | PIN_OSPEED_HIGH(GPIOI_PIN7) | PIN_OSPEED_HIGH(GPIOI_PIN8) | PIN_OSPEED_HIGH(GPIOI_PIN9) | PIN_OSPEED_HIGH(GPIOI_PIN10) | PIN_OSPEED_HIGH(GPIOI_PIN11) | PIN_OSPEED_HIGH(GPIOI_PIN12) | PIN_OSPEED_HIGH(GPIOI_PIN13) | PIN_OSPEED_HIGH(GPIOI_PIN14) | PIN_OSPEED_HIGH(GPIOI_PIN15))
#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | PIN_PUPDR_PULLUP(GPIOI_PIN1) | PIN_PUPDR_PULLUP(GPIOI_PIN2) | PIN_PUPDR_PULLUP(GPIOI_PIN3) | PIN_PUPDR_PULLUP(GPIOI_PIN4) | PIN_PUPDR_PULLUP(GPIOI_PIN5) | PIN_PUPDR_PULLUP(GPIOI_PIN6) | PIN_PUPDR_PULLUP(GPIOI_PIN7) | PIN_PUPDR_PULLUP(GPIOI_PIN8) | PIN_PUPDR_PULLUP(GPIOI_PIN9) | PIN_PUPDR_PULLUP(GPIOI_PIN10) | PIN_PUPDR_PULLUP(GPIOI_PIN11) | PIN_PUPDR_PULLUP(GPIOI_PIN12) | PIN_PUPDR_PULLUP(GPIOI_PIN13) | PIN_PUPDR_PULLUP(GPIOI_PIN14) | PIN_PUPDR_PULLUP(GPIOI_PIN15))
#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | PIN_ODR_HIGH(GPIOI_PIN1) | PIN_ODR_HIGH(GPIOI_PIN2) | PIN_ODR_HIGH(GPIOI_PIN3) | PIN_ODR_HIGH(GPIOI_PIN4) | PIN_ODR_HIGH(GPIOI_PIN5) | PIN_ODR_HIGH(GPIOI_PIN6) | PIN_ODR_HIGH(GPIOI_PIN7) | PIN_ODR_HIGH(GPIOI_PIN8) | PIN_ODR_HIGH(GPIOI_PIN9) | PIN_ODR_HIGH(GPIOI_PIN10) | PIN_ODR_HIGH(GPIOI_PIN11) | PIN_ODR_HIGH(GPIOI_PIN12) | PIN_ODR_HIGH(GPIOI_PIN13) | PIN_ODR_HIGH(GPIOI_PIN14) | PIN_ODR_HIGH(GPIOI_PIN15))
#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | PIN_AFIO_AF(GPIOI_PIN1, 0U) | PIN_AFIO_AF(GPIOI_PIN2, 0U) | PIN_AFIO_AF(GPIOI_PIN3, 0U) | PIN_AFIO_AF(GPIOI_PIN4, 0U) | PIN_AFIO_AF(GPIOI_PIN5, 0U) | PIN_AFIO_AF(GPIOI_PIN6, 0U) | PIN_AFIO_AF(GPIOI_PIN7, 0U))
#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | PIN_AFIO_AF(GPIOI_PIN9, 0U) | PIN_AFIO_AF(GPIOI_PIN10, 0U) | PIN_AFIO_AF(GPIOI_PIN11, 0U) | PIN_AFIO_AF(GPIOI_PIN12, 0U) | PIN_AFIO_AF(GPIOI_PIN13, 0U) | PIN_AFIO_AF(GPIOI_PIN14, 0U) | PIN_AFIO_AF(GPIOI_PIN15, 0U))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* BOARD_H */

1193
drivers/boards/BLACKPILL_STM32_F411/cfg/board.chcfg
View File

File diff suppressed because it is too large Load Diff

15
drivers/boards/BLACKPILL_STM32_F411/cfg/board.fmpp
Unescape View File

@ -1,15 +0,0 @@
sourceRoot: ../../../../../tools/ftl/processors/boards/stm32f4xx/templates
outputRoot: ..
dataRoot: .
freemarkerLinks: {
lib: ../../../../../tools/ftl/libs
}
data : {
doc1:xml (
board.chcfg
{
}
)
}

703
drivers/boards/GENERIC_STM32_F072XB/cfg/board.chcfg
Unescape View File

@ -1,703 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- STM32F0xx board Template -->
<board
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f0xx_board.xsd">
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f0xx/templates</templates_path>
<output_path>..</output_path>
<hal_version>5.0.x</hal_version>
</configuration_settings>
<board_name>ST STM32F072B-Discovery</board_name>
<board_id>ST_STM32F072B_DISCOVERY</board_id>
<board_functions></board_functions>
<subtype>STM32F072xB</subtype>
<clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0"
LSEBypass="false" LSEDrive="3 High Drive (default)" />
<ports>
<GPIOA>
<pin0
ID="BUTTON"
Type="PushPull"
Speed="Minimum"
Resistor="Floating"
Level="High"
Mode="Input"
Alternate="0" />
<pin1
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin2
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin3
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin4
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin5
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin6
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin7
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin8
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin9
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin10
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin11
ID="USB_DM"
Type="PushPull"
Speed="Minimum"
Resistor="Floating"
Level="High"
Mode="Input"
Alternate="0" />
<pin12
ID="USB_DP"
Type="PushPull"
Speed="Minimum"
Resistor="Floating"
Level="High"
Mode="Input"
Alternate="0" />
<pin13
ID="SWDIO"
Type="PushPull"
Speed="Maximum"
Resistor="PullUp"
Level="High"
Mode="Alternate"
Alternate="0" />
<pin14
ID="SWCLK"
Type="PushPull"
Speed="Maximum"
Resistor="PullDown"
Level="High"
Mode="Alternate"
Alternate="0" />
<pin15
ID=""
Type="PushPull"
Speed="Maximum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
</GPIOA>
<GPIOB>
<pin0
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin1
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin2
ID=""
Type="PushPull"
Speed="Maximum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin3
ID=""
Type="PushPull"
Speed="Maximum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin4
ID=""
Type="PushPull"
Speed="Maximum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin5
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin6
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin7
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin8
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin9
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin10
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin11
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin12
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin13
ID="SPI2_SCK"
Type="PushPull"
Speed="Minimum"
Resistor="Floating"
Level="High"
Mode="Alternate"
Alternate="0" />
<pin14
ID="SPI2_MISO"
Type="PushPull"
Speed="Minimum"
Resistor="Floating"
Level="High"
Mode="Alternate"
Alternate="0" />
<pin15
ID="SPI2_MOSI"
Type="PushPull"
Speed="Minimum"
Resistor="Floating"
Level="High"
Mode="Alternate"
Alternate="0" />
</GPIOB>
<GPIOC>
<pin0
ID="MEMS_CS"
Type="PushPull"
Speed="Maximum"
Resistor="Floating"
Level="High"
Mode="Output"
Alternate="0" />
<pin1
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin2
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin3
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin4
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin5
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin6
ID="LED_RED"
Type="PushPull"
Speed="Maximum"
Resistor="Floating"
Level="Low"
Mode="Output"
Alternate="0" />
<pin7
ID="LED_BLUE"
Type="PushPull"
Speed="Maximum"
Resistor="Floating"
Level="Low"
Mode="Output"
Alternate="0" />
<pin8
ID="LED_ORANGE"
Type="PushPull"
Speed="Maximum"
Resistor="Floating"
Level="Low"
Mode="Output"
Alternate="0" ></pin8>
<pin9
ID="LED_GREEN"
Type="PushPull"
Speed="Maximum"
Resistor="Floating"
Level="Low"
Mode="Output"
Alternate="0" />
<pin10
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin11
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin12
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin13
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin14
ID="OSC32_IN"
Type="PushPull"
Speed="Maximum"
Resistor="Floating"
Level="High"
Mode="Input"
Alternate="0" />
<pin15
ID="OSC32_OUT"
Type="PushPull"
Speed="Maximum"
Resistor="Floating"
Level="High"
Mode="Input"
Alternate="0" />
</GPIOC>
<GPIOD>
<pin0
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin1
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin2
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin3
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin4
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin5
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin6
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin7
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin8
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin9
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin10
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin11
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin12
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin13
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin14
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin15
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
</GPIOD>
<GPIOE>
<pin0 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin1 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin2 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin3 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin4 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin5 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin6 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin7 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin8 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin9 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin10 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin11 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin12 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin13 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin14 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
<pin15 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
Level="High" Mode="Input" Alternate="0" />
</GPIOE>
<GPIOF>
<pin0
ID="OSC_IN"
Type="PushPull"
Speed="Minimum"
Resistor="Floating"
Level="High"
Mode="Input"
Alternate="0" />
<pin1
ID="OSC_OUT"
Type="PushPull"
Speed="Minimum"
Resistor="Floating"
Level="High"
Mode="Input"
Alternate="0" />
<pin2
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin3
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin4
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin5
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin6
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin7
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin8
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin9
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin10
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin11
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin12
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin13
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin14
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
<pin15
ID=""
Type="PushPull"
Speed="Minimum"
Resistor="PullUp"
Level="High"
Mode="Input"
Alternate="0" />
</GPIOF>
</ports>
</board>

15
drivers/boards/GENERIC_STM32_F072XB/cfg/board.fmpp
Unescape View File

@ -1,15 +0,0 @@
sourceRoot: ../../../../../tools/ftl/processors/boards/stm32f0xx/templates
outputRoot: ..
dataRoot: .
freemarkerLinks: {
lib: ../../../../../tools/ftl/libs
}
data : {
doc1:xml (
board.chcfg
{
}
)
}

5
drivers/boards/GENERIC_STM32_F303XC/board.mk
Unescape View File

@ -1,5 +0,0 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/boards/GENERIC_STM32_F303XC/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/boards/GENERIC_STM32_F303XC

5
drivers/boards/IC_TEENSY_3_1/board.mk
Unescape View File

@ -1,5 +0,0 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/boards/IC_TEENSY_3_1/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/boards/IC_TEENSY_3_1

5
drivers/boards/STM32_F103_STM32DUINO/board.mk
Unescape View File

@ -1,5 +0,0 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/boards/STM32_F103_STM32DUINO/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/boards/STM32_F103_STM32DUINO

537
keyboards/handwired/onekey/blackpill_f401/halconf.h
Unescape View File

@ -1,525 +1,20 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
/* Copyright 2020 Nick Brassel (tzarc)
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_0_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL FALSE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB TRUE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS FALSE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#pragma once
#endif /* HALCONF_H */
#define HAL_USE_I2C TRUE
/** @} */
#include_next "halconf.h"

264
keyboards/handwired/onekey/blackpill_f401/mcuconf.h
Unescape View File

@ -1,253 +1,21 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
/* Copyright 2020 Nick Brassel (tzarc)
*
* IRQ priorities:
* 15...0 Lowest...Highest.
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
#pragma once
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#include_next "mcuconf.h"
#endif /* MCUCONF_H */
#undef STM32_I2C_USE_I2C1
#define STM32_I2C_USE_I2C1 TRUE

537
keyboards/handwired/onekey/blackpill_f411/halconf.h
Unescape View File

@ -1,525 +1,20 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
/* Copyright 2020 Nick Brassel (tzarc)
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_0_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL FALSE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB TRUE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS FALSE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#pragma once
#endif /* HALCONF_H */
#define HAL_USE_I2C TRUE
/** @} */
#include_next "halconf.h"

264
keyboards/handwired/onekey/blackpill_f411/mcuconf.h
Unescape View File

@ -1,253 +1,21 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
/* Copyright 2020 Nick Brassel (tzarc)
*
* IRQ priorities:
* 15...0 Lowest...Highest.
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 384
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 8
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
#pragma once
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#include_next "mcuconf.h"
#endif /* MCUCONF_H */
#undef STM32_I2C_USE_I2C1
#define STM32_I2C_USE_I2C1 TRUE

268
keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.c
Unescape View File

@ -1,268 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#include "stm32_gpio.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief Type of STM32 GPIO port setup.
*/
typedef struct {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
/**
* @brief Type of STM32 GPIO initialization data.
*/
typedef struct {
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
gpio_setup_t PFData;
#endif
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
gpio_setup_t PGData;
#endif
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
gpio_setup_t PHData;
#endif
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
gpio_setup_t PIData;
#endif
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
gpio_setup_t PJData;
#endif
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
gpio_setup_t PKData;
#endif
} gpio_config_t;
/**
* @brief STM32 GPIO static initialization data.
*/
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
#endif
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB(STM32_GPIO_EN_MASK);
rccEnableAHB(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
#if STM32_HAS_GPIOF
gpio_init(GPIOF, &gpio_default_config.PFData);
#endif
#if STM32_HAS_GPIOG
gpio_init(GPIOG, &gpio_default_config.PGData);
#endif
#if STM32_HAS_GPIOH
gpio_init(GPIOH, &gpio_default_config.PHData);
#endif
#if STM32_HAS_GPIOI
gpio_init(GPIOI, &gpio_default_config.PIData);
#endif
#if STM32_HAS_GPIOJ
gpio_init(GPIOJ, &gpio_default_config.PJData);
#endif
#if STM32_HAS_GPIOK
gpio_init(GPIOK, &gpio_default_config.PKData);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Early initialization code.
* @details GPIO ports and system clocks are initialized before everything
* else.
*/
void __early_init(void) {
extern void enter_bootloader_mode_if_requested(void);
enter_bootloader_mode_if_requested();
stm32_gpio_init();
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}

5
keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.mk
Unescape View File

@ -1,5 +0,0 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6

896
keyboards/vinta/boards/GENERIC_STM32_F042X6/board.h
Unescape View File

@ -1,896 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H
#define _BOARD_H
/*
* Setup for STMicroelectronics STM32 Nucleo32-F042K6 board.
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_STM32_F042X6
#define BOARD_NAME "Vinta PCB"
/*
* Board oscillators-related settings.
* NOTE: LSE not fitted.
* NOTE: HSE not fitted.
*/
#if !defined(STM32_LSECLK)
#define STM32_LSECLK 0U
#endif
#define STM32_LSEDRV (3U << 3U)
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 0U
#endif
/*
* MCU type as defined in the ST header.
*/
#define STM32F042x6
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN3 3U
#define GPIOC_PIN4 4U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_PIN0 0U
#define GPIOD_PIN1 1U
#define GPIOD_PIN2 2U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_PIN12 12U
#define GPIOD_PIN13 13U
#define GPIOD_PIN14 14U
#define GPIOD_PIN15 15U
#define GPIOE_PIN0 0U
#define GPIOE_PIN1 1U
#define GPIOE_PIN2 2U
#define GPIOE_PIN3 3U
#define GPIOE_PIN4 4U
#define GPIOE_PIN5 5U
#define GPIOE_PIN6 6U
#define GPIOE_PIN7 7U
#define GPIOE_PIN8 8U
#define GPIOE_PIN9 9U
#define GPIOE_PIN10 10U
#define GPIOE_PIN11 11U
#define GPIOE_PIN12 12U
#define GPIOE_PIN13 13U
#define GPIOE_PIN14 14U
#define GPIOE_PIN15 15U
#define GPIOF_PIN0 0U
#define GPIOF_PIN1 1U
#define GPIOF_PIN2 2U
#define GPIOF_PIN3 3U
#define GPIOF_PIN4 4U
#define GPIOF_PIN5 5U
#define GPIOF_PIN6 6U
#define GPIOF_PIN7 7U
#define GPIOF_PIN8 8U
#define GPIOF_PIN9 9U
#define GPIOF_PIN10 10U
#define GPIOF_PIN11 11U
#define GPIOF_PIN12 12U
#define GPIOF_PIN13 13U
#define GPIOF_PIN14 14U
#define GPIOF_PIN15 15U
/*
* IO lines assignments.
*/
#define LINE_BOOT0 PAL_LINE(GPIOB, 8U)
#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the STM32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
#define PIN_ODR_LOW(n) (0U << (n))
#define PIN_ODR_HIGH(n) (1U << (n))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
/*
* GPIOA setup:
*
* PA0 - COL5
* PA1 - COL4
* PA2 - COL3
* PA3 - COL2
* PA4 - COL1
* PA5 - COL0
* PA6 - ROW4
* PA7 - ROW3
* PA8 - NC
* PA9 - ROW1
* PA10 - ROW0
* PA11 - USB_DM
* PA12 - USB_DP
* PA13 - COL15/SWDIO (for now, COL15)
* PA14 - COL14/SWCLK (for now, COL14)
* PA15 - COL13
*/
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
PIN_MODE_INPUT(GPIOA_PIN1) | \
PIN_MODE_INPUT(GPIOA_PIN2) | \
PIN_MODE_INPUT(GPIOA_PIN3) | \
PIN_MODE_INPUT(GPIOA_PIN4) | \
PIN_MODE_INPUT(GPIOA_PIN5) | \
PIN_MODE_INPUT(GPIOA_PIN6) | \
PIN_MODE_INPUT(GPIOA_PIN7) | \
PIN_MODE_INPUT(GPIOA_PIN8) | \
PIN_MODE_INPUT(GPIOA_PIN9) | \
PIN_MODE_INPUT(GPIOA_PIN10) | \
PIN_MODE_INPUT(GPIOA_PIN11) | \
PIN_MODE_INPUT(GPIOA_PIN12) | \
PIN_MODE_INPUT(GPIOA_PIN13) | \
PIN_MODE_INPUT(GPIOA_PIN14) | \
PIN_MODE_INPUT(GPIOA_PIN15))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN2) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN7) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN8) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN9) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN10) | \
PIN_OSPEED_HIGH(GPIOA_PIN11) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN12) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN13) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN14) | \
PIN_OSPEED_VERYLOW(GPIOA_PIN15))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
PIN_PUPDR_FLOATING(GPIOA_PIN11) | \
PIN_PUPDR_FLOATING(GPIOA_PIN12) | \
PIN_PUPDR_PULLUP(GPIOA_PIN13) | \
PIN_PUPDR_PULLUP(GPIOA_PIN14) | \
PIN_PUPDR_PULLUP(GPIOA_PIN15))
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
PIN_ODR_HIGH(GPIOA_PIN1) | \
PIN_ODR_HIGH(GPIOA_PIN2) | \
PIN_ODR_HIGH(GPIOA_PIN3) | \
PIN_ODR_HIGH(GPIOA_PIN4) | \
PIN_ODR_HIGH(GPIOA_PIN5) | \
PIN_ODR_HIGH(GPIOA_PIN6) | \
PIN_ODR_HIGH(GPIOA_PIN7) | \
PIN_ODR_HIGH(GPIOA_PIN8) | \
PIN_ODR_HIGH(GPIOA_PIN9) | \
PIN_ODR_HIGH(GPIOA_PIN10) | \
PIN_ODR_HIGH(GPIOA_PIN11) | \
PIN_ODR_HIGH(GPIOA_PIN12) | \
PIN_ODR_HIGH(GPIOA_PIN13) | \
PIN_ODR_HIGH(GPIOA_PIN14) | \
PIN_ODR_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
PIN_AFIO_AF(GPIOA_PIN2, 0U) | \
PIN_AFIO_AF(GPIOA_PIN3, 0U) | \
PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
PIN_AFIO_AF(GPIOA_PIN5, 0U) | \
PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
PIN_AFIO_AF(GPIOA_PIN7, 0U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \
PIN_AFIO_AF(GPIOA_PIN9, 0U) | \
PIN_AFIO_AF(GPIOA_PIN10, 0U) | \
PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
PIN_AFIO_AF(GPIOA_PIN13, 0U) | \
PIN_AFIO_AF(GPIOA_PIN14, 0U) | \
PIN_AFIO_AF(GPIOA_PIN15, 0U))
/*
* GPIOB setup:
*
* PB0 - ROW2
* PB1 - RGB_D
* PB2 - PIN2 (input pullup).
* PB3 - COL12
* PB4 - COL11
* PB5 - COL10
* PB6 - COL9
* PB7 - COL8
* PB8 - BOOT0 (set as output for STM32F042)
* PB9 - PIN9 (input pullup).
* PB10 - PIN10 (input pullup).
* PB11 - PIN11 (input pullup).
* PB12 - PIN12 (input pullup).
* PB13 - PIN13 (input pullup).
* PB14 - PIN14 (input pullup).
* PB15 - PIN15 (input pullup).
*/
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
PIN_MODE_OUTPUT(GPIOB_PIN1) | \
PIN_MODE_INPUT(GPIOB_PIN2) | \
PIN_MODE_INPUT(GPIOB_PIN3) | \
PIN_MODE_INPUT(GPIOB_PIN4) | \
PIN_MODE_INPUT(GPIOB_PIN5) | \
PIN_MODE_INPUT(GPIOB_PIN6) | \
PIN_MODE_INPUT(GPIOB_PIN7) | \
PIN_MODE_OUTPUT(GPIOB_PIN8) | \
PIN_MODE_INPUT(GPIOB_PIN9) | \
PIN_MODE_INPUT(GPIOB_PIN10) | \
PIN_MODE_INPUT(GPIOB_PIN11) | \
PIN_MODE_INPUT(GPIOB_PIN12) | \
PIN_MODE_INPUT(GPIOB_PIN13) | \
PIN_MODE_INPUT(GPIOB_PIN14) | \
PIN_MODE_INPUT(GPIOB_PIN15))
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | \
PIN_OSPEED_HIGH(GPIOB_PIN1) | \
PIN_OSPEED_HIGH(GPIOB_PIN2) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN3) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \
PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \
PIN_OSPEED_HIGH(GPIOB_PIN9) | \
PIN_OSPEED_HIGH(GPIOB_PIN10) | \
PIN_OSPEED_HIGH(GPIOB_PIN11) | \
PIN_OSPEED_HIGH(GPIOB_PIN12) | \
PIN_OSPEED_HIGH(GPIOB_PIN13) | \
PIN_OSPEED_HIGH(GPIOB_PIN14) | \
PIN_OSPEED_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
PIN_PUPDR_FLOATING(GPIOB_PIN1) | \
PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
PIN_PUPDR_PULLUP(GPIOB_PIN3) | \
PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
PIN_PUPDR_PULLDOWN(GPIOB_PIN8) | \
PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
PIN_PUPDR_PULLUP(GPIOB_PIN15))
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
PIN_ODR_HIGH(GPIOB_PIN1) | \
PIN_ODR_HIGH(GPIOB_PIN2) | \
PIN_ODR_HIGH(GPIOB_PIN3) | \
PIN_ODR_HIGH(GPIOB_PIN4) | \
PIN_ODR_HIGH(GPIOB_PIN5) | \
PIN_ODR_HIGH(GPIOB_PIN6) | \
PIN_ODR_HIGH(GPIOB_PIN7) | \
PIN_ODR_HIGH(GPIOB_PIN8) | \
PIN_ODR_HIGH(GPIOB_PIN9) | \
PIN_ODR_HIGH(GPIOB_PIN10) | \
PIN_ODR_HIGH(GPIOB_PIN11) | \
PIN_ODR_HIGH(GPIOB_PIN12) | \
PIN_ODR_HIGH(GPIOB_PIN13) | \
PIN_ODR_HIGH(GPIOB_PIN14) | \
PIN_ODR_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
PIN_AFIO_AF(GPIOB_PIN3, 0U) | \
PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
PIN_AFIO_AF(GPIOB_PIN7, 0U))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
PIN_AFIO_AF(GPIOB_PIN15, 0U))
/*
* GPIOC setup:
*
* PC0 - PIN0 (input pullup).
* PC1 - PIN1 (input pullup).
* PC2 - PIN2 (input pullup).
* PC3 - PIN3 (input pullup).
* PC4 - PIN4 (input pullup).
* PC5 - PIN5 (input pullup).
* PC6 - PIN6 (input pullup).
* PC7 - PIN7 (input pullup).
* PC8 - PIN8 (input pullup).
* PC9 - PIN9 (input pullup).
* PC10 - PIN10 (input pullup).
* PC11 - PIN11 (input pullup).
* PC12 - PIN12 (input pullup).
* PC13 - PIN13 (input pullup).
* PC14 - PIN14 (input pullup).
* PC15 - PIN15 (input pullup).
*/
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
PIN_MODE_INPUT(GPIOC_PIN1) | \
PIN_MODE_INPUT(GPIOC_PIN2) | \
PIN_MODE_INPUT(GPIOC_PIN3) | \
PIN_MODE_INPUT(GPIOC_PIN4) | \
PIN_MODE_INPUT(GPIOC_PIN5) | \
PIN_MODE_INPUT(GPIOC_PIN6) | \
PIN_MODE_INPUT(GPIOC_PIN7) | \
PIN_MODE_INPUT(GPIOC_PIN8) | \
PIN_MODE_INPUT(GPIOC_PIN9) | \
PIN_MODE_INPUT(GPIOC_PIN10) | \
PIN_MODE_INPUT(GPIOC_PIN11) | \
PIN_MODE_INPUT(GPIOC_PIN12) | \
PIN_MODE_INPUT(GPIOC_PIN13) | \
PIN_MODE_INPUT(GPIOC_PIN14) | \
PIN_MODE_INPUT(GPIOC_PIN15))
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \
PIN_OSPEED_HIGH(GPIOC_PIN1) | \
PIN_OSPEED_HIGH(GPIOC_PIN2) | \
PIN_OSPEED_HIGH(GPIOC_PIN3) | \
PIN_OSPEED_HIGH(GPIOC_PIN4) | \
PIN_OSPEED_HIGH(GPIOC_PIN5) | \
PIN_OSPEED_HIGH(GPIOC_PIN6) | \
PIN_OSPEED_HIGH(GPIOC_PIN7) | \
PIN_OSPEED_HIGH(GPIOC_PIN8) | \
PIN_OSPEED_HIGH(GPIOC_PIN9) | \
PIN_OSPEED_HIGH(GPIOC_PIN10) | \
PIN_OSPEED_HIGH(GPIOC_PIN11) | \
PIN_OSPEED_HIGH(GPIOC_PIN12) | \
PIN_OSPEED_HIGH(GPIOC_PIN13) | \
PIN_OSPEED_HIGH(GPIOC_PIN14) | \
PIN_OSPEED_HIGH(GPIOC_PIN15))
#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
PIN_PUPDR_PULLUP(GPIOC_PIN15))
#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
PIN_ODR_HIGH(GPIOC_PIN1) | \
PIN_ODR_HIGH(GPIOC_PIN2) | \
PIN_ODR_HIGH(GPIOC_PIN3) | \
PIN_ODR_HIGH(GPIOC_PIN4) | \
PIN_ODR_HIGH(GPIOC_PIN5) | \
PIN_ODR_HIGH(GPIOC_PIN6) | \
PIN_ODR_HIGH(GPIOC_PIN7) | \
PIN_ODR_HIGH(GPIOC_PIN8) | \
PIN_ODR_HIGH(GPIOC_PIN9) | \
PIN_ODR_HIGH(GPIOC_PIN10) | \
PIN_ODR_HIGH(GPIOC_PIN11) | \
PIN_ODR_HIGH(GPIOC_PIN12) | \
PIN_ODR_HIGH(GPIOC_PIN13) | \
PIN_ODR_HIGH(GPIOC_PIN14) | \
PIN_ODR_HIGH(GPIOC_PIN15))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
PIN_AFIO_AF(GPIOC_PIN1, 0U) | \
PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
PIN_AFIO_AF(GPIOC_PIN7, 0U))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
PIN_AFIO_AF(GPIOC_PIN13, 0U) | \
PIN_AFIO_AF(GPIOC_PIN14, 0U) | \
PIN_AFIO_AF(GPIOC_PIN15, 0U))
/*
* GPIOD setup:
*
* PD0 - PIN0 (input pullup).
* PD1 - PIN1 (input pullup).
* PD2 - PIN2 (input pullup).
* PD3 - PIN3 (input pullup).
* PD4 - PIN4 (input pullup).
* PD5 - PIN5 (input pullup).
* PD6 - PIN6 (input pullup).
* PD7 - PIN7 (input pullup).
* PD8 - PIN8 (input pullup).
* PD9 - PIN9 (input pullup).
* PD10 - PIN10 (input pullup).
* PD11 - PIN11 (input pullup).
* PD12 - PIN12 (input pullup).
* PD13 - PIN13 (input pullup).
* PD14 - PIN14 (input pullup).
* PD15 - PIN15 (input pullup).
*/
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
PIN_MODE_INPUT(GPIOD_PIN1) | \
PIN_MODE_INPUT(GPIOD_PIN2) | \
PIN_MODE_INPUT(GPIOD_PIN3) | \
PIN_MODE_INPUT(GPIOD_PIN4) | \
PIN_MODE_INPUT(GPIOD_PIN5) | \
PIN_MODE_INPUT(GPIOD_PIN6) | \
PIN_MODE_INPUT(GPIOD_PIN7) | \
PIN_MODE_INPUT(GPIOD_PIN8) | \
PIN_MODE_INPUT(GPIOD_PIN9) | \
PIN_MODE_INPUT(GPIOD_PIN10) | \
PIN_MODE_INPUT(GPIOD_PIN11) | \
PIN_MODE_INPUT(GPIOD_PIN12) | \
PIN_MODE_INPUT(GPIOD_PIN13) | \
PIN_MODE_INPUT(GPIOD_PIN14) | \
PIN_MODE_INPUT(GPIOD_PIN15))
#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \
PIN_OSPEED_HIGH(GPIOD_PIN1) | \
PIN_OSPEED_HIGH(GPIOD_PIN2) | \
PIN_OSPEED_HIGH(GPIOD_PIN3) | \
PIN_OSPEED_HIGH(GPIOD_PIN4) | \
PIN_OSPEED_HIGH(GPIOD_PIN5) | \
PIN_OSPEED_HIGH(GPIOD_PIN6) | \
PIN_OSPEED_HIGH(GPIOD_PIN7) | \
PIN_OSPEED_HIGH(GPIOD_PIN8) | \
PIN_OSPEED_HIGH(GPIOD_PIN9) | \
PIN_OSPEED_HIGH(GPIOD_PIN10) | \
PIN_OSPEED_HIGH(GPIOD_PIN11) | \
PIN_OSPEED_HIGH(GPIOD_PIN12) | \
PIN_OSPEED_HIGH(GPIOD_PIN13) | \
PIN_OSPEED_HIGH(GPIOD_PIN14) | \
PIN_OSPEED_HIGH(GPIOD_PIN15))
#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
PIN_PUPDR_PULLUP(GPIOD_PIN15))
#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
PIN_ODR_HIGH(GPIOD_PIN1) | \
PIN_ODR_HIGH(GPIOD_PIN2) | \
PIN_ODR_HIGH(GPIOD_PIN3) | \
PIN_ODR_HIGH(GPIOD_PIN4) | \
PIN_ODR_HIGH(GPIOD_PIN5) | \
PIN_ODR_HIGH(GPIOD_PIN6) | \
PIN_ODR_HIGH(GPIOD_PIN7) | \
PIN_ODR_HIGH(GPIOD_PIN8) | \
PIN_ODR_HIGH(GPIOD_PIN9) | \
PIN_ODR_HIGH(GPIOD_PIN10) | \
PIN_ODR_HIGH(GPIOD_PIN11) | \
PIN_ODR_HIGH(GPIOD_PIN12) | \
PIN_ODR_HIGH(GPIOD_PIN13) | \
PIN_ODR_HIGH(GPIOD_PIN14) | \
PIN_ODR_HIGH(GPIOD_PIN15))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
PIN_AFIO_AF(GPIOD_PIN7, 0U))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
PIN_AFIO_AF(GPIOD_PIN15, 0U))
/*
* GPIOE setup:
*
* PE0 - PIN0 (input pullup).
* PE1 - PIN1 (input pullup).
* PE2 - PIN2 (input pullup).
* PE3 - PIN3 (input pullup).
* PE4 - PIN4 (input pullup).
* PE5 - PIN5 (input pullup).
* PE6 - PIN6 (input pullup).
* PE7 - PIN7 (input pullup).
* PE8 - PIN8 (input pullup).
* PE9 - PIN9 (input pullup).
* PE10 - PIN10 (input pullup).
* PE11 - PIN11 (input pullup).
* PE12 - PIN12 (input pullup).
* PE13 - PIN13 (input pullup).
* PE14 - PIN14 (input pullup).
* PE15 - PIN15 (input pullup).
*/
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
PIN_MODE_INPUT(GPIOE_PIN1) | \
PIN_MODE_INPUT(GPIOE_PIN2) | \
PIN_MODE_INPUT(GPIOE_PIN3) | \
PIN_MODE_INPUT(GPIOE_PIN4) | \
PIN_MODE_INPUT(GPIOE_PIN5) | \
PIN_MODE_INPUT(GPIOE_PIN6) | \
PIN_MODE_INPUT(GPIOE_PIN7) | \
PIN_MODE_INPUT(GPIOE_PIN8) | \
PIN_MODE_INPUT(GPIOE_PIN9) | \
PIN_MODE_INPUT(GPIOE_PIN10) | \
PIN_MODE_INPUT(GPIOE_PIN11) | \
PIN_MODE_INPUT(GPIOE_PIN12) | \
PIN_MODE_INPUT(GPIOE_PIN13) | \
PIN_MODE_INPUT(GPIOE_PIN14) | \
PIN_MODE_INPUT(GPIOE_PIN15))
#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \
PIN_OSPEED_HIGH(GPIOE_PIN1) | \
PIN_OSPEED_HIGH(GPIOE_PIN2) | \
PIN_OSPEED_HIGH(GPIOE_PIN3) | \
PIN_OSPEED_HIGH(GPIOE_PIN4) | \
PIN_OSPEED_HIGH(GPIOE_PIN5) | \
PIN_OSPEED_HIGH(GPIOE_PIN6) | \
PIN_OSPEED_HIGH(GPIOE_PIN7) | \
PIN_OSPEED_HIGH(GPIOE_PIN8) | \
PIN_OSPEED_HIGH(GPIOE_PIN9) | \
PIN_OSPEED_HIGH(GPIOE_PIN10) | \
PIN_OSPEED_HIGH(GPIOE_PIN11) | \
PIN_OSPEED_HIGH(GPIOE_PIN12) | \
PIN_OSPEED_HIGH(GPIOE_PIN13) | \
PIN_OSPEED_HIGH(GPIOE_PIN14) | \
PIN_OSPEED_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
PIN_PUPDR_PULLUP(GPIOE_PIN15))
#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
PIN_ODR_HIGH(GPIOE_PIN1) | \
PIN_ODR_HIGH(GPIOE_PIN2) | \
PIN_ODR_HIGH(GPIOE_PIN3) | \
PIN_ODR_HIGH(GPIOE_PIN4) | \
PIN_ODR_HIGH(GPIOE_PIN5) | \
PIN_ODR_HIGH(GPIOE_PIN6) | \
PIN_ODR_HIGH(GPIOE_PIN7) | \
PIN_ODR_HIGH(GPIOE_PIN8) | \
PIN_ODR_HIGH(GPIOE_PIN9) | \
PIN_ODR_HIGH(GPIOE_PIN10) | \
PIN_ODR_HIGH(GPIOE_PIN11) | \
PIN_ODR_HIGH(GPIOE_PIN12) | \
PIN_ODR_HIGH(GPIOE_PIN13) | \
PIN_ODR_HIGH(GPIOE_PIN14) | \
PIN_ODR_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
PIN_AFIO_AF(GPIOE_PIN7, 0U))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
PIN_AFIO_AF(GPIOE_PIN15, 0U))
/*
* GPIOF setup:
*
* PF0 - COL7
* PF1 - COL6
* PF2 - PIN2 (input pullup).
* PF3 - PIN3 (input pullup).
* PF4 - PIN4 (input pullup).
* PF5 - PIN5 (input pullup).
* PF6 - PIN6 (input pullup).
* PF7 - PIN7 (input pullup).
* PF8 - PIN8 (input pullup).
* PF9 - PIN9 (input pullup).
* PF10 - PIN10 (input pullup).
* PF11 - PIN11 (input pullup).
* PF12 - PIN12 (input pullup).
* PF13 - PIN13 (input pullup).
* PF14 - PIN14 (input pullup).
* PF15 - PIN15 (input pullup).
*/
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
PIN_MODE_INPUT(GPIOF_PIN1) | \
PIN_MODE_INPUT(GPIOF_PIN2) | \
PIN_MODE_INPUT(GPIOF_PIN3) | \
PIN_MODE_INPUT(GPIOF_PIN4) | \
PIN_MODE_INPUT(GPIOF_PIN5) | \
PIN_MODE_INPUT(GPIOF_PIN6) | \
PIN_MODE_INPUT(GPIOF_PIN7) | \
PIN_MODE_INPUT(GPIOF_PIN8) | \
PIN_MODE_INPUT(GPIOF_PIN9) | \
PIN_MODE_INPUT(GPIOF_PIN10) | \
PIN_MODE_INPUT(GPIOF_PIN11) | \
PIN_MODE_INPUT(GPIOF_PIN12) | \
PIN_MODE_INPUT(GPIOF_PIN13) | \
PIN_MODE_INPUT(GPIOF_PIN14) | \
PIN_MODE_INPUT(GPIOF_PIN15))
#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \
PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \
PIN_OSPEED_HIGH(GPIOF_PIN2) | \
PIN_OSPEED_HIGH(GPIOF_PIN3) | \
PIN_OSPEED_HIGH(GPIOF_PIN4) | \
PIN_OSPEED_HIGH(GPIOF_PIN5) | \
PIN_OSPEED_HIGH(GPIOF_PIN6) | \
PIN_OSPEED_HIGH(GPIOF_PIN7) | \
PIN_OSPEED_HIGH(GPIOF_PIN8) | \
PIN_OSPEED_HIGH(GPIOF_PIN9) | \
PIN_OSPEED_HIGH(GPIOF_PIN10) | \
PIN_OSPEED_HIGH(GPIOF_PIN11) | \
PIN_OSPEED_HIGH(GPIOF_PIN12) | \
PIN_OSPEED_HIGH(GPIOF_PIN13) | \
PIN_OSPEED_HIGH(GPIOF_PIN14) | \
PIN_OSPEED_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \
PIN_PUPDR_PULLUP(GPIOF_PIN1) | \
PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
PIN_PUPDR_PULLUP(GPIOF_PIN15))
#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
PIN_ODR_HIGH(GPIOF_PIN1) | \
PIN_ODR_HIGH(GPIOF_PIN2) | \
PIN_ODR_HIGH(GPIOF_PIN3) | \
PIN_ODR_HIGH(GPIOF_PIN4) | \
PIN_ODR_HIGH(GPIOF_PIN5) | \
PIN_ODR_HIGH(GPIOF_PIN6) | \
PIN_ODR_HIGH(GPIOF_PIN7) | \
PIN_ODR_HIGH(GPIOF_PIN8) | \
PIN_ODR_HIGH(GPIOF_PIN9) | \
PIN_ODR_HIGH(GPIOF_PIN10) | \
PIN_ODR_HIGH(GPIOF_PIN11) | \
PIN_ODR_HIGH(GPIOF_PIN12) | \
PIN_ODR_HIGH(GPIOF_PIN13) | \
PIN_ODR_HIGH(GPIOF_PIN14) | \
PIN_ODR_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
PIN_AFIO_AF(GPIOF_PIN7, 0U))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
PIN_AFIO_AF(GPIOF_PIN15, 0U))
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H */

5
keyboards/vinta/boards/GENERIC_STM32_F042X6/board.mk
Unescape View File

@ -1,5 +0,0 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/boards/GENERIC_STM32_F042X6

7
keyboards/vinta/bootloader_defs.h
Unescape View File

@ -1,7 +0,0 @@
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up here:
* http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
* This also requires a patch to chibios:
* <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch
*/
#define STM32_BOOTLOADER_ADDRESS 0x1FFFC400

4
lib/python/qmk/cli/cformat.py
Unescape View File

@ -43,8 +43,8 @@ def cformat(cli):
# Empty array for files
files = []
# Core directories for formatting
core_dirs = ['drivers', 'quantum', 'tests', 'tmk_core']
ignores = ['tmk_core/protocol/usb_hid', 'quantum/template']
core_dirs = ['drivers', 'quantum', 'tests', 'tmk_core', 'platforms']
ignores = ['tmk_core/protocol/usb_hid', 'quantum/template', 'platforms/chibios']
# Find the list of files to format
if cli.args.files:
files.extend(normpath(file) for file in cli.args.files)

9
platforms/chibios/BLACKPILL_STM32_F401/board/board.mk
Unescape View File

@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

20
platforms/chibios/BLACKPILL_STM32_F401/configs/board.h
Unescape View File

@ -0,0 +1,20 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next "board.h"
#undef STM32_HSE_BYPASS

0
keyboards/handwired/onekey/blackpill_f401/chconf.h → platforms/chibios/BLACKPILL_STM32_F401/configs/chconf.h
Unescape View File

23
platforms/chibios/BLACKPILL_STM32_F401/configs/config.h
Unescape View File

@ -0,0 +1,23 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define BOARD_OTG_NOVBUSSENS 1
#define STM32_LSECLK 32768U
#define STM32_HSECLK 25000000U
#define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE

525
platforms/chibios/BLACKPILL_STM32_F401/configs/halconf.h
Unescape View File

@ -0,0 +1,525 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_0_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL FALSE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB TRUE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS FALSE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* HALCONF_H */
/** @} */

253
platforms/chibios/BLACKPILL_STM32_F401/configs/mcuconf.h
Unescape View File

@ -0,0 +1,253 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/BLACKPILL_STM32_F411/board/board.mk
Unescape View File

@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

20
platforms/chibios/BLACKPILL_STM32_F411/configs/board.h
Unescape View File

@ -0,0 +1,20 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next "board.h"
#undef STM32_HSE_BYPASS

0
keyboards/handwired/onekey/blackpill_f411/chconf.h → platforms/chibios/BLACKPILL_STM32_F411/configs/chconf.h
Unescape View File

23
platforms/chibios/BLACKPILL_STM32_F411/configs/config.h
Unescape View File

@ -0,0 +1,23 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define BOARD_OTG_NOVBUSSENS 1
#define STM32_LSECLK 32768U
#define STM32_HSECLK 25000000U
#define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE

525
platforms/chibios/BLACKPILL_STM32_F411/configs/halconf.h
Unescape View File

@ -0,0 +1,525 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_0_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL FALSE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB TRUE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS FALSE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* HALCONF_H */
/** @} */

253
platforms/chibios/BLACKPILL_STM32_F411/configs/mcuconf.h
Unescape View File

@ -0,0 +1,253 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 384
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 8
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI21_PRIORITY 15
#define STM32_IRQ_EXTI22_PRIORITY 15
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_USE_SPI3 FALSE
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

3
keyboards/vinta/boards/GENERIC_STM32_F042X6/board.c → platforms/chibios/GENERIC_STM32_F042X6/board/board.c
Unescape View File

@ -202,13 +202,14 @@ static void stm32_gpio_init(void) {
/* Driver exported functions. */
/*===========================================================================*/
__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {}
/**
* @brief Early initialization code.
* @details GPIO ports and system clocks are initialized before everything
* else.
*/
void __early_init(void) {
extern void enter_bootloader_mode_if_requested(void);
enter_bootloader_mode_if_requested();
stm32_gpio_init();

0
keyboards/peiorisboards/ixora/boards/GENERIC_STM32_F042X6/board.h → platforms/chibios/GENERIC_STM32_F042X6/board/board.h
Unescape View File

4
drivers/boards/GENERIC_STM32_F072XB/board.mk → platforms/chibios/GENERIC_STM32_F042X6/board/board.mk
Unescape View File

@ -1,8 +1,8 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/boards/GENERIC_STM32_F072XB/board.c
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/boards/GENERIC_STM32_F072XB
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)

0
keyboards/peiorisboards/ixora/bootloader_defs.h → platforms/chibios/GENERIC_STM32_F042X6/configs/bootloader_defs.h
Unescape View File

0
drivers/boards/GENERIC_STM32_F072XB/board.c → platforms/chibios/GENERIC_STM32_F072XB/board/board.c
Unescape View File

0
drivers/boards/GENERIC_STM32_F072XB/board.h → platforms/chibios/GENERIC_STM32_F072XB/board/board.h
Unescape View File

4
drivers/boards/BLACKPILL_STM32_F411/board.mk → platforms/chibios/GENERIC_STM32_F072XB/board/board.mk
Unescape View File

@ -1,8 +1,8 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/boards/BLACKPILL_STM32_F411/board.c
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/boards/BLACKPILL_STM32_F411
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)

0
drivers/boards/GENERIC_STM32_F072XB/bootloader_defs.h → platforms/chibios/GENERIC_STM32_F072XB/configs/bootloader_defs.h
Unescape View File

2
drivers/boards/GENERIC_STM32_F303XC/board.c → platforms/chibios/GENERIC_STM32_F303XC/board/board.c
Unescape View File

@ -181,7 +181,7 @@ static void stm32_gpio_init(void) {
#endif
}
void enter_bootloader_mode_if_requested(void);
__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {}
/**
* @brief Early initialization code.

0
drivers/boards/GENERIC_STM32_F303XC/board.h → platforms/chibios/GENERIC_STM32_F303XC/board/board.h
Unescape View File

4
drivers/boards/BLACKPILL_STM32_F401/board.mk → platforms/chibios/GENERIC_STM32_F303XC/board/board.mk
Unescape View File

@ -1,8 +1,8 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/boards/BLACKPILL_STM32_F401/board.c
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/boards/BLACKPILL_STM32_F401
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)

0
drivers/boards/GENERIC_STM32_F303XC/bootloader_defs.h → platforms/chibios/GENERIC_STM32_F303XC/configs/bootloader_defs.h
Unescape View File

362
quantum/stm32/chconf.h → platforms/chibios/GENERIC_STM32_F303XC/configs/chconf.h
Unescape View File

@ -26,10 +26,10 @@
*/
#ifndef CHCONF_H
# define CHCONF_H
#define CHCONF_H
# define _CHIBIOS_RT_CONF_
# define _CHIBIOS_RT_CONF_VER_6_0_
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_6_0_
/*===========================================================================*/
/**
@ -42,34 +42,34 @@
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
# if !defined(CH_CFG_ST_RESOLUTION)
# define CH_CFG_ST_RESOLUTION 32
# endif
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
# if !defined(CH_CFG_ST_FREQUENCY)
# define CH_CFG_ST_FREQUENCY 100000
# endif
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 100000
#endif
/**
* @brief Time intervals data size.
* @note Allowed values are 16, 32 or 64 bits.
*/
# if !defined(CH_CFG_INTERVALS_SIZE)
# define CH_CFG_INTERVALS_SIZE 32
# endif
#if !defined(CH_CFG_INTERVALS_SIZE)
#define CH_CFG_INTERVALS_SIZE 32
#endif
/**
* @brief Time types data size.
* @note Allowed values are 16 or 32 bits.
*/
# if !defined(CH_CFG_TIME_TYPES_SIZE)
# define CH_CFG_TIME_TYPES_SIZE 32
# endif
#if !defined(CH_CFG_TIME_TYPES_SIZE)
#define CH_CFG_TIME_TYPES_SIZE 32
#endif
/**
* @brief Time delta constant for the tick-less mode.
@ -79,9 +79,9 @@
* The value one is not valid, timeouts are rounded up to
* this value.
*/
# if !defined(CH_CFG_ST_TIMEDELTA)
# define CH_CFG_ST_TIMEDELTA 2
# endif
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 2
#endif
/** @} */
@ -104,9 +104,9 @@
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/
# if !defined(CH_CFG_TIME_QUANTUM)
# define CH_CFG_TIME_QUANTUM 0
# endif
#if !defined(CH_CFG_TIME_QUANTUM)
#define CH_CFG_TIME_QUANTUM 0
#endif
/**
* @brief Managed RAM size.
@ -119,9 +119,9 @@
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
# if !defined(CH_CFG_MEMCORE_SIZE)
# define CH_CFG_MEMCORE_SIZE 0
# endif
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
@ -130,9 +130,9 @@
* function becomes the idle thread and must implement an
* infinite loop.
*/
# if !defined(CH_CFG_NO_IDLE_THREAD)
# define CH_CFG_NO_IDLE_THREAD FALSE
# endif
#if !defined(CH_CFG_NO_IDLE_THREAD)
#define CH_CFG_NO_IDLE_THREAD FALSE
#endif
/** @} */
@ -151,9 +151,9 @@
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_OPTIMIZE_SPEED)
# define CH_CFG_OPTIMIZE_SPEED TRUE
# endif
#if !defined(CH_CFG_OPTIMIZE_SPEED)
#define CH_CFG_OPTIMIZE_SPEED TRUE
#endif
/** @} */
@ -171,9 +171,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_TM)
# define CH_CFG_USE_TM TRUE
# endif
#if !defined(CH_CFG_USE_TM)
#define CH_CFG_USE_TM TRUE
#endif
/**
* @brief Threads registry APIs.
@ -181,9 +181,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_REGISTRY)
# define CH_CFG_USE_REGISTRY TRUE
# endif
#if !defined(CH_CFG_USE_REGISTRY)
#define CH_CFG_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
@ -192,9 +192,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_WAITEXIT)
# define CH_CFG_USE_WAITEXIT TRUE
# endif
#if !defined(CH_CFG_USE_WAITEXIT)
#define CH_CFG_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
@ -202,9 +202,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_SEMAPHORES)
# define CH_CFG_USE_SEMAPHORES TRUE
# endif
#if !defined(CH_CFG_USE_SEMAPHORES)
#define CH_CFG_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
@ -215,9 +215,9 @@
* requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
# if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
# define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
# endif
#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Mutexes APIs.
@ -225,9 +225,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_MUTEXES)
# define CH_CFG_USE_MUTEXES TRUE
# endif
#if !defined(CH_CFG_USE_MUTEXES)
#define CH_CFG_USE_MUTEXES TRUE
#endif
/**
* @brief Enables recursive behavior on mutexes.
@ -237,9 +237,9 @@
* @note The default is @p FALSE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
# if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
# define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
# endif
#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
#endif
/**
* @brief Conditional Variables APIs.
@ -249,9 +249,9 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
# if !defined(CH_CFG_USE_CONDVARS)
# define CH_CFG_USE_CONDVARS TRUE
# endif
#if !defined(CH_CFG_USE_CONDVARS)
#define CH_CFG_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
@ -261,9 +261,9 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_CONDVARS.
*/
# if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
# define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
# endif
#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
@ -271,9 +271,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_EVENTS)
# define CH_CFG_USE_EVENTS TRUE
# endif
#if !defined(CH_CFG_USE_EVENTS)
#define CH_CFG_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
@ -283,9 +283,9 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_EVENTS.
*/
# if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
# define CH_CFG_USE_EVENTS_TIMEOUT TRUE
# endif
#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
@ -294,9 +294,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_MESSAGES)
# define CH_CFG_USE_MESSAGES TRUE
# endif
#if !defined(CH_CFG_USE_MESSAGES)
#define CH_CFG_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
@ -307,9 +307,9 @@
* requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/
# if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
# define CH_CFG_USE_MESSAGES_PRIORITY TRUE
# endif
#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
#define CH_CFG_USE_MESSAGES_PRIORITY TRUE
#endif
/**
* @brief Mailboxes APIs.
@ -319,9 +319,9 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
# if !defined(CH_CFG_USE_MAILBOXES)
# define CH_CFG_USE_MAILBOXES TRUE
# endif
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
@ -330,9 +330,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_MEMCORE)
# define CH_CFG_USE_MEMCORE TRUE
# endif
#if !defined(CH_CFG_USE_MEMCORE)
#define CH_CFG_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
@ -344,9 +344,9 @@
* @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
# if !defined(CH_CFG_USE_HEAP)
# define CH_CFG_USE_HEAP TRUE
# endif
#if !defined(CH_CFG_USE_HEAP)
#define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief Memory Pools Allocator APIs.
@ -355,9 +355,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_MEMPOOLS)
# define CH_CFG_USE_MEMPOOLS TRUE
# endif
#if !defined(CH_CFG_USE_MEMPOOLS)
#define CH_CFG_USE_MEMPOOLS TRUE
#endif
/**
* @brief Objects FIFOs APIs.
@ -366,9 +366,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_OBJ_FIFOS)
# define CH_CFG_USE_OBJ_FIFOS TRUE
# endif
#if !defined(CH_CFG_USE_OBJ_FIFOS)
#define CH_CFG_USE_OBJ_FIFOS TRUE
#endif
/**
* @brief Pipes APIs.
@ -377,9 +377,9 @@
*
* @note The default is @p TRUE.
*/
# if !defined(CH_CFG_USE_PIPES)
# define CH_CFG_USE_PIPES TRUE
# endif
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES TRUE
#endif
/**
* @brief Dynamic Threads APIs.
@ -390,9 +390,9 @@
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
# if !defined(CH_CFG_USE_DYNAMIC)
# define CH_CFG_USE_DYNAMIC TRUE
# endif
#if !defined(CH_CFG_USE_DYNAMIC)
#define CH_CFG_USE_DYNAMIC TRUE
#endif
/** @} */
@ -410,60 +410,60 @@
*
* @note The default is @p FALSE.
*/
# if !defined(CH_CFG_USE_FACTORY)
# define CH_CFG_USE_FACTORY TRUE
# endif
#if !defined(CH_CFG_USE_FACTORY)
#define CH_CFG_USE_FACTORY TRUE
#endif
/**
* @brief Maximum length for object names.
* @details If the specified length is zero then the name is stored by
* pointer but this could have unintended side effects.
*/
# if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
# define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
# endif
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
#endif
/**
* @brief Enables the registry of generic objects.
*/
# if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
# define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
# endif
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
#endif
/**
* @brief Enables factory for generic buffers.
*/
# if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
# define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
# endif
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
#endif
/**
* @brief Enables factory for semaphores.
*/
# if !defined(CH_CFG_FACTORY_SEMAPHORES)
# define CH_CFG_FACTORY_SEMAPHORES TRUE
# endif
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
#define CH_CFG_FACTORY_SEMAPHORES TRUE
#endif
/**
* @brief Enables factory for mailboxes.
*/
# if !defined(CH_CFG_FACTORY_MAILBOXES)
# define CH_CFG_FACTORY_MAILBOXES TRUE
# endif
#if !defined(CH_CFG_FACTORY_MAILBOXES)
#define CH_CFG_FACTORY_MAILBOXES TRUE
#endif
/**
* @brief Enables factory for objects FIFOs.
*/
# if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
# define CH_CFG_FACTORY_OBJ_FIFOS TRUE
# endif
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
#endif
/**
* @brief Enables factory for Pipes.
*/
# if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
# define CH_CFG_FACTORY_PIPES TRUE
# endif
#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
#define CH_CFG_FACTORY_PIPES TRUE
#endif
/** @} */
@ -479,9 +479,9 @@
*
* @note The default is @p FALSE.
*/
# if !defined(CH_DBG_STATISTICS)
# define CH_DBG_STATISTICS FALSE
# endif
#if !defined(CH_DBG_STATISTICS)
#define CH_DBG_STATISTICS FALSE
#endif
/**
* @brief Debug option, system state check.
@ -490,9 +490,9 @@
*
* @note The default is @p FALSE.
*/
# if !defined(CH_DBG_SYSTEM_STATE_CHECK)
# define CH_DBG_SYSTEM_STATE_CHECK FALSE
# endif
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
@ -501,9 +501,9 @@
*
* @note The default is @p FALSE.
*/
# if !defined(CH_DBG_ENABLE_CHECKS)
# define CH_DBG_ENABLE_CHECKS FALSE
# endif
#if !defined(CH_DBG_ENABLE_CHECKS)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
@ -513,9 +513,9 @@
*
* @note The default is @p FALSE.
*/
# if !defined(CH_DBG_ENABLE_ASSERTS)
# define CH_DBG_ENABLE_ASSERTS FALSE
# endif
#if !defined(CH_DBG_ENABLE_ASSERTS)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
@ -523,18 +523,18 @@
*
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
# if !defined(CH_DBG_TRACE_MASK)
# define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
# endif
#if !defined(CH_DBG_TRACE_MASK)
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
#endif
/**
* @brief Trace buffer entries.
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
* different from @p CH_DBG_TRACE_MASK_DISABLED.
*/
# if !defined(CH_DBG_TRACE_BUFFER_SIZE)
# define CH_DBG_TRACE_BUFFER_SIZE 128
# endif
#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
#define CH_DBG_TRACE_BUFFER_SIZE 128
#endif
/**
* @brief Debug option, stack checks.
@ -546,9 +546,9 @@
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
# if !defined(CH_DBG_ENABLE_STACK_CHECK)
# define CH_DBG_ENABLE_STACK_CHECK TRUE
# endif
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
#define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif
/**
* @brief Debug option, stacks initialization.
@ -558,9 +558,9 @@
*
* @note The default is @p FALSE.
*/
# if !defined(CH_DBG_FILL_THREADS)
# define CH_DBG_FILL_THREADS FALSE
# endif
#if !defined(CH_DBG_FILL_THREADS)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
@ -571,9 +571,9 @@
* @note This debug option is not currently compatible with the
* tickless mode.
*/
# if !defined(CH_DBG_THREADS_PROFILING)
# define CH_DBG_THREADS_PROFILING FALSE
# endif
#if !defined(CH_DBG_THREADS_PROFILING)
#define CH_DBG_THREADS_PROFILING FALSE
#endif
/** @} */
@ -588,22 +588,24 @@
* @brief System structure extension.
* @details User fields added to the end of the @p ch_system_t structure.
*/
# define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add threads custom fields here.*/
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief System initialization hook.
* @details User initialization code added to the @p chSysInit() function
* just before interrupts are enabled globally.
*/
# define CH_CFG_SYSTEM_INIT_HOOK() \
{ /* Add threads initialization code here.*/ \
}
#define CH_CFG_SYSTEM_INIT_HOOK() { \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
# define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/
#define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
@ -612,39 +614,39 @@
* @note It is invoked from within @p _thread_init() and implicitly from all
* the threads creation APIs.
*/
# define CH_CFG_THREAD_INIT_HOOK(tp) \
{ /* Add threads initialization code here.*/ \
}
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
# define CH_CFG_THREAD_EXIT_HOOK(tp) \
{ /* Add threads finalization code here.*/ \
}
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
# define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \
{ /* Context switch code here.*/ \
}
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* Context switch code here.*/ \
}
/**
* @brief ISR enter hook.
*/
# define CH_CFG_IRQ_PROLOGUE_HOOK() \
{ /* IRQ prologue code here.*/ \
}
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
/* IRQ prologue code here.*/ \
}
/**
* @brief ISR exit hook.
*/
# define CH_CFG_IRQ_EPILOGUE_HOOK() \
{ /* IRQ epilogue code here.*/ \
}
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
/* IRQ epilogue code here.*/ \
}
/**
* @brief Idle thread enter hook.
@ -652,9 +654,9 @@
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
# define CH_CFG_IDLE_ENTER_HOOK() \
{ /* Idle-enter code here.*/ \
}
#define CH_CFG_IDLE_ENTER_HOOK() { \
/* Idle-enter code here.*/ \
}
/**
* @brief Idle thread leave hook.
@ -662,44 +664,44 @@
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
# define CH_CFG_IDLE_LEAVE_HOOK() \
{ /* Idle-leave code here.*/ \
}
#define CH_CFG_IDLE_LEAVE_HOOK() { \
/* Idle-leave code here.*/ \
}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
# define CH_CFG_IDLE_LOOP_HOOK() \
{ /* Idle loop code here.*/ \
}
#define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
# define CH_CFG_SYSTEM_TICK_HOOK() \
{ /* System tick event code here.*/ \
}
#define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \
}
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
# define CH_CFG_SYSTEM_HALT_HOOK(reason) \
{ /* System halt code here.*/ \
}
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
/**
* @brief Trace hook.
* @details This hook is invoked each time a new record is written in the
* trace buffer.
*/
# define CH_CFG_TRACE_HOOK(tep) \
{ /* Trace code here.*/ \
}
#define CH_CFG_TRACE_HOOK(tep) { \
/* Trace code here.*/ \
}
/** @} */
@ -707,6 +709,6 @@
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* CHCONF_H */
#endif /* CHCONF_H */
/** @} */

339
quantum/stm32/halconf.h → platforms/chibios/GENERIC_STM32_F303XC/configs/halconf.h
Unescape View File

@ -26,173 +26,173 @@
*/
#ifndef HALCONF_H
# define HALCONF_H
#define HALCONF_H
# define _CHIBIOS_HAL_CONF_
# define _CHIBIOS_HAL_CONF_VER_7_0_
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_0_
# include "mcuconf.h"
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
# if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
# define HAL_USE_PAL TRUE
# endif
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
# if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
# define HAL_USE_ADC FALSE
# endif
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
# if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
# define HAL_USE_CAN FALSE
# endif
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
# if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
# define HAL_USE_CRY FALSE
# endif
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
# if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
# define HAL_USE_DAC TRUE
# endif
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC TRUE
#endif
/**
* @brief Enables the GPT subsystem.
*/
# if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
# define HAL_USE_GPT TRUE
# endif
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT TRUE
#endif
/**
* @brief Enables the I2C subsystem.
*/
# if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
# define HAL_USE_I2C TRUE
# endif
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C TRUE
#endif
/**
* @brief Enables the I2S subsystem.
*/
# if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
# define HAL_USE_I2S FALSE
# endif
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
# if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
# define HAL_USE_ICU FALSE
# endif
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
# if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
# define HAL_USE_MAC FALSE
# endif
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
# if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
# define HAL_USE_MMC_SPI FALSE
# endif
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
# if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
# define HAL_USE_PWM TRUE
# endif
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM TRUE
#endif
/**
* @brief Enables the RTC subsystem.
*/
# if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
# define HAL_USE_RTC FALSE
# endif
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
# if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
# define HAL_USE_SDC FALSE
# endif
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
# if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
# define HAL_USE_SERIAL FALSE
# endif
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL FALSE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
# if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
# define HAL_USE_SERIAL_USB TRUE
# endif
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB TRUE
#endif
/**
* @brief Enables the SIO subsystem.
*/
# if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
# define HAL_USE_SIO FALSE
# endif
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
# if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
# define HAL_USE_SPI TRUE
# endif
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI TRUE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
# if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
# define HAL_USE_TRNG FALSE
# endif
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
# if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
# define HAL_USE_UART FALSE
# endif
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
# if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
# define HAL_USE_USB TRUE
# endif
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB TRUE
#endif
/**
* @brief Enables the WDG subsystem.
*/
# if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
# define HAL_USE_WDG FALSE
# endif
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
# if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
# define HAL_USE_WSPI FALSE
# endif
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
@ -202,17 +202,17 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
# define PAL_USE_CALLBACKS TRUE
# endif
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS TRUE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
# define PAL_USE_WAIT TRUE
# endif
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
@ -222,17 +222,17 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
# define ADC_USE_WAIT TRUE
# endif
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
# define ADC_USE_MUTUAL_EXCLUSION TRUE
# endif
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
@ -241,16 +241,16 @@
/**
* @brief Sleep mode related APIs inclusion switch.
*/
# if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
# define CAN_USE_SLEEP_MODE TRUE
# endif
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
# if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
# define CAN_ENFORCE_USE_CALLBACKS FALSE
# endif
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
@ -263,16 +263,16 @@
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
# if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
# define HAL_CRY_USE_FALLBACK FALSE
# endif
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
# if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
# define HAL_CRY_ENFORCE_FALLBACK FALSE
# endif
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
@ -282,17 +282,17 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
# define DAC_USE_WAIT TRUE
# endif
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
# define DAC_USE_MUTUAL_EXCLUSION TRUE
# endif
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
@ -301,9 +301,9 @@
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
# if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
# define I2C_USE_MUTUAL_EXCLUSION TRUE
# endif
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
@ -312,16 +312,16 @@
/**
* @brief Enables the zero-copy API.
*/
# if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
# define MAC_USE_ZERO_COPY FALSE
# endif
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
# if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
# define MAC_USE_EVENTS TRUE
# endif
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
@ -335,9 +335,9 @@
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
# if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
# define MMC_NICE_WAITING TRUE
# endif
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
@ -347,18 +347,18 @@
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
# if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
# define SDC_INIT_RETRY 100
# endif
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
# if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
# define SDC_MMC_SUPPORT FALSE
# endif
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
@ -366,23 +366,23 @@
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
# if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
# define SDC_NICE_WAITING TRUE
# endif
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
# if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
# define SDC_INIT_OCR_V20 0x50FF8000U
# endif
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
# if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
# define SDC_INIT_OCR 0x80100000U
# endif
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
@ -393,9 +393,9 @@
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
# if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
# define SERIAL_DEFAULT_BITRATE 38400
# endif
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
@ -404,9 +404,9 @@
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
# if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
# define SERIAL_BUFFERS_SIZE 16
# endif
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
@ -419,17 +419,17 @@
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
# if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
# define SERIAL_USB_BUFFERS_SIZE 1
# endif
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 1
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
# if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
# define SERIAL_USB_BUFFERS_NUMBER 2
# endif
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
@ -439,33 +439,34 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
# define SPI_USE_WAIT TRUE
# endif
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
# define SPI_USE_CIRCULAR FALSE
# endif
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
# define SPI_USE_MUTUAL_EXCLUSION TRUE
# endif
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
# if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
# define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
# endif
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
@ -475,17 +476,17 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
# define UART_USE_WAIT FALSE
# endif
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
# define UART_USE_MUTUAL_EXCLUSION FALSE
# endif
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
@ -495,9 +496,9 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
# define USB_USE_WAIT TRUE
# endif
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
@ -507,17 +508,17 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
# define WSPI_USE_WAIT TRUE
# endif
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
# if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
# define WSPI_USE_MUTUAL_EXCLUSION TRUE
# endif
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* HALCONF_H */

273
platforms/chibios/GENERIC_STM32_F303XC/configs/mcuconf.h
Unescape View File

@ -0,0 +1,273 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F3xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F3xx_MCUCONF
#define STM32F303_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PREDIV_VALUE 1
#define STM32_PLLMUL_VALUE 9
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_USART2SW STM32_USART2SW_PCLK
#define STM32_USART3SW STM32_USART3SW_PCLK
#define STM32_UART4SW STM32_UART4SW_PCLK
#define STM32_UART5SW STM32_UART5SW_PCLK
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_USB_CLOCK_REQUIRED TRUE
#define STM32_USBPRE STM32_USBPRE_DIV1P5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 15
#define STM32_IRQ_EXTI20_PRIORITY 15
#define STM32_IRQ_EXTI21_22_29_PRIORITY 6
#define STM32_IRQ_EXTI30_32_PRIORITY 6
#define STM32_IRQ_EXTI33_PRIORITY 6
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_USE_ADC4 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 TRUE
#define STM32_DAC_USE_DAC1_CH2 TRUE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM6 TRUE
#define STM32_GPT_USE_TIM7 TRUE
#define STM32_GPT_USE_TIM8 TRUE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 TRUE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_IRQ_PRIORITY 10
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
#define STM32_I2C_USE_DMA TRUE
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#define STM32_I2C_I2C2_DMA_PRIORITY 1
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 TRUE
#define STM32_PWM_USE_TIM4 TRUE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 TRUE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

9
platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk
Unescape View File

@ -0,0 +1,9 @@
# Proton C MCU settings for converting AVR projects
MCU = STM32F303
# These are defaults based on what has been implemented for ARM boards
AUDIO_ENABLE = yes
WS2812_DRIVER = bitbang
# Force task driven PWM until ARM can provide automatic configuration
BACKLIGHT_DRIVER = software

0
drivers/boards/IC_TEENSY_3_1/board.c → platforms/chibios/IC_TEENSY_3_1/board/board.c
Unescape View File

0
drivers/boards/IC_TEENSY_3_1/board.h → platforms/chibios/IC_TEENSY_3_1/board/board.h
Unescape View File

9
platforms/chibios/IC_TEENSY_3_1/board/board.mk
Unescape View File

@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

3
drivers/boards/STM32_F103_STM32DUINO/board.c → platforms/chibios/STM32_F103_STM32DUINO/board/board.c
Unescape View File

@ -35,12 +35,15 @@ const PALConfig pal_default_config =
};
#endif
__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {}
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
enter_bootloader_mode_if_requested();
stm32_clock_init();
}

0
drivers/boards/STM32_F103_STM32DUINO/board.h → platforms/chibios/STM32_F103_STM32DUINO/board/board.h
Unescape View File

9
platforms/chibios/STM32_F103_STM32DUINO/board/board.mk
Unescape View File

@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

20
platforms/chibios/keyboard-config-templates/board.h
Unescape View File

@ -0,0 +1,20 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next "board.h"
// #undef STM32_HSE_BYPASS

20
platforms/chibios/keyboard-config-templates/chconf.h
Unescape View File

@ -0,0 +1,20 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
// #define CH_CFG_OPTIMIZE_SPEED TRUE
#include_next "chconf.h"

20
platforms/chibios/keyboard-config-templates/halconf.h
Unescape View File

@ -0,0 +1,20 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
// #define HAL_USE_DAC TRUE
#include_next "halconf.h"

21
platforms/chibios/keyboard-config-templates/mcuconf.h
Unescape View File

@ -0,0 +1,21 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next "mcuconf.h"
// #undef STM32_HSE_ENABLED
// #define STM32_HSE_ENABLED FALSE

0
drivers/boards/ld/MKL26Z64.ld → platforms/chibios/ld/MKL26Z64.ld
Unescape View File

0
drivers/boards/ld/STM32F103x8_stm32duino_bootloader.ld → platforms/chibios/ld/STM32F103x8_stm32duino_bootloader.ld
Unescape View File

273
quantum/stm32/mcuconf.h
Unescape View File

@ -1,273 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F3xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F3xx_MCUCONF
#define STM32F303_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PREDIV_VALUE 1
#define STM32_PLLMUL_VALUE 9
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_USART2SW STM32_USART2SW_PCLK
#define STM32_USART3SW STM32_USART3SW_PCLK
#define STM32_UART4SW STM32_UART4SW_PCLK
#define STM32_UART5SW STM32_UART5SW_PCLK
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_USB_CLOCK_REQUIRED TRUE
#define STM32_USBPRE STM32_USBPRE_DIV1P5
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 15
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 15
#define STM32_IRQ_EXTI20_PRIORITY 15
#define STM32_IRQ_EXTI21_22_29_PRIORITY 6
#define STM32_IRQ_EXTI30_32_PRIORITY 6
#define STM32_IRQ_EXTI33_PRIORITY 6
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_USE_ADC4 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 TRUE
#define STM32_DAC_USE_DAC1_CH2 TRUE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM6 TRUE
#define STM32_GPT_USE_TIM7 TRUE
#define STM32_GPT_USE_TIM8 TRUE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 TRUE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_IRQ_PRIORITY 10
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
#define STM32_I2C_USE_DMA TRUE
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#define STM32_I2C_I2C2_DMA_PRIORITY 1
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 TRUE
#define STM32_PWM_USE_TIM4 TRUE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 TRUE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 TRUE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

47
quantum/stm32/proton_c.mk
Unescape View File

@ -1,47 +0,0 @@
# Proton C MCU settings for converting AVR projects
# These are defaults based on what has been implemented for ARM boards
AUDIO_ENABLE = yes
WS2812_DRIVER = bitbang
# Force task driven PWM until ARM can provide automatic configuration
BACKLIGHT_DRIVER = software
# The rest of these settings shouldn't change
## chip/board settings
# - the next two should match the directories in
# <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
MCU_FAMILY = STM32
MCU_SERIES = STM32F3xx
# Linker script to use
# - it should exist either in <chibios>/os/common/ports/ARMCMx/compilers/GCC/ld/
# or <this_dir>/ld/
MCU_LDSCRIPT = STM32F303xC
# Startup code to use
# - it should exist in <chibios>/os/common/startup/ARMCMx/compilers/GCC/mk/
MCU_STARTUP = stm32f3xx
# Board: it should exist either in <chibios>/os/hal/boards/
# or <this_dir>/boards
BOARD = GENERIC_STM32_F303XC
# Cortex version
MCU = cortex-m4
# ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
ARMV = 7
USE_FPU = yes
# Vector table for application
# 0x00000000-0x00001000 area is occupied by bootlaoder.*/
# The CORTEX_VTOR... is needed only for MCHCK/Infinity KB
# OPT_DEFS = -DCORTEX_VTOR_INIT=0x08005000
OPT_DEFS =
# Options to pass to dfu-util when flashing
DFU_ARGS = -d 0483:df11 -a 0 -s 0x08000000:leave
DFU_SUFFIX_ARGS = -p df11 -v 0483

113
tmk_core/chibios.mk
Unescape View File

@ -50,11 +50,42 @@ PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)/$(PLAT
endif
include $(PLATFORM_MK)
BOARD_MK :=
ifneq ("$(wildcard $(KEYBOARD_PATH_5)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_5)
BOARD_MK += $(KEYBOARD_PATH_5)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_4)
BOARD_MK += $(KEYBOARD_PATH_4)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_3)
BOARD_MK += $(KEYBOARD_PATH_3)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_2)
BOARD_MK += $(KEYBOARD_PATH_2)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_1)
BOARD_MK += $(KEYBOARD_PATH_1)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/$(BOARD)/board/board.mk)","")
BOARD_PATH = $(TOP_DIR)/platforms/chibios/$(BOARD)
BOARD_MK += $(TOP_DIR)/platforms/chibios/$(BOARD)/board/board.mk
KEYBOARD_PATHS += $(BOARD_PATH)/configs
endif
ifeq ("$(wildcard $(BOARD_MK))","")
BOARD_MK = $(CHIBIOS)/os/hal/boards/$(BOARD)/board.mk
ifeq ("$(wildcard $(BOARD_MK))","")
BOARD_MK = $(CHIBIOS_CONTRIB)/os/hal/boards/$(BOARD)/board.mk
endif
endif
# Bootloader address
ifdef STM32_BOOTLOADER_ADDRESS
OPT_DEFS += -DSTM32_BOOTLOADER_ADDRESS=$(STM32_BOOTLOADER_ADDRESS)
endif
# Work out if we need to set up the include for the bootloader definitions
ifneq ("$(wildcard $(KEYBOARD_PATH_5)/bootloader_defs.h)","")
OPT_DEFS += -include $(KEYBOARD_PATH_5)/bootloader_defs.h
else ifneq ("$(wildcard $(KEYBOARD_PATH_5)/boards/$(BOARD)/bootloader_defs.h)","")
@ -75,38 +106,52 @@ else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/bootloader_defs.h)","")
OPT_DEFS += -include $(KEYBOARD_PATH_1)/bootloader_defs.h
else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/boards/$(BOARD)/bootloader_defs.h)","")
OPT_DEFS += -include $(KEYBOARD_PATH_1)/boards/$(BOARD)/bootloader_defs.h
else ifneq ("$(wildcard $(TOP_DIR)/drivers/boards/$(BOARD)/bootloader_defs.h)","")
OPT_DEFS += -include $(TOP_DIR)/drivers/boards/$(BOARD)/bootloader_defs.h
else ifneq ("$(wildcard $(BOARD_PATH)/configs/bootloader_defs.h)","")
OPT_DEFS += -include $(BOARD_PATH)/configs/bootloader_defs.h
endif
BOARD_MK :=
# Work out the config file directories
ifneq ("$(wildcard $(KEYBOARD_PATH_5)/chconf.h)","")
CHCONFDIR = $(KEYBOARD_PATH_5)
else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/chconf.h)","")
CHCONFDIR = $(KEYBOARD_PATH_4)
else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/chconf.h)","")
CHCONFDIR = $(KEYBOARD_PATH_3)
else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/chconf.h)","")
CHCONFDIR = $(KEYBOARD_PATH_2)
else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/chconf.h)","")
CHCONFDIR = $(KEYBOARD_PATH_1)
else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/$(BOARD)/configs/chconf.h)","")
CHCONFDIR = $(TOP_DIR)/platforms/chibios/$(BOARD)/configs
endif
ifneq ("$(wildcard $(KEYBOARD_PATH_5)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_5)
BOARD_MK += $(KEYBOARD_PATH_5)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_4)
BOARD_MK += $(KEYBOARD_PATH_4)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_3)
BOARD_MK += $(KEYBOARD_PATH_3)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_2)
BOARD_MK += $(KEYBOARD_PATH_2)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(KEYBOARD_PATH_1)
BOARD_MK += $(KEYBOARD_PATH_1)/boards/$(BOARD)/board.mk
else ifneq ("$(wildcard $(TOP_DIR)/drivers/boards/$(BOARD)/board.mk)","")
BOARD_PATH = $(TOP_DIR)/drivers
BOARD_MK += $(TOP_DIR)/drivers/boards/$(BOARD)/board.mk
ifneq ("$(wildcard $(KEYBOARD_PATH_5)/halconf.h)","")
HALCONFDIR = $(KEYBOARD_PATH_5)
else ifneq ("$(wildcard $(KEYBOARD_PATH_4)/halconf.h)","")
HALCONFDIR = $(KEYBOARD_PATH_4)
else ifneq ("$(wildcard $(KEYBOARD_PATH_3)/halconf.h)","")
HALCONFDIR = $(KEYBOARD_PATH_3)
else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/halconf.h)","")
HALCONFDIR = $(KEYBOARD_PATH_2)
else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/halconf.h)","")
HALCONFDIR = $(KEYBOARD_PATH_1)
else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/$(BOARD)/configs/halconf.h)","")
HALCONFDIR = $(TOP_DIR)/platforms/chibios/$(BOARD)/configs
endif
ifeq ("$(wildcard $(BOARD_MK))","")
BOARD_MK = $(CHIBIOS)/os/hal/boards/$(BOARD)/board.mk
ifeq ("$(wildcard $(BOARD_MK))","")
BOARD_MK = $(CHIBIOS_CONTRIB)/os/hal/boards/$(BOARD)/board.mk
endif
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
ifeq ("$(PLATFORM_NAME)","")
PLATFORM_NAME = platform
endif
PLATFORM_MK = $(CHIBIOS)/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
ifeq ("$(wildcard $(PLATFORM_MK))","")
PLATFORM_MK = $(CHIBIOS_CONTRIB)/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)/$(PLATFORM_NAME).mk
endif
include $(PLATFORM_MK)
include $(BOARD_MK)
-include $(CHIBIOS)/os/hal/osal/rt/osal.mk # ChibiOS <= 19.x
@ -138,8 +183,8 @@ else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/ld/$(MCU_LDSCRIPT).ld)","")
LDSCRIPT = $(KEYBOARD_PATH_2)/ld/$(MCU_LDSCRIPT).ld
else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/ld/$(MCU_LDSCRIPT).ld)","")
LDSCRIPT = $(KEYBOARD_PATH_1)/ld/$(MCU_LDSCRIPT).ld
else ifneq ("$(wildcard $(TOP_DIR)/drivers/boards/ld/$(MCU_LDSCRIPT).ld)","")
LDSCRIPT = $(TOP_DIR)/drivers/boards/ld/$(MCU_LDSCRIPT).ld
else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/ld/$(MCU_LDSCRIPT).ld)","")
LDSCRIPT = $(TOP_DIR)/platforms/chibios/ld/$(MCU_LDSCRIPT).ld
else ifneq ("$(wildcard $(STARTUPLD_CONTRIB)/$(MCU_LDSCRIPT).ld)","")
LDSCRIPT = $(STARTUPLD_CONTRIB)/$(MCU_LDSCRIPT).ld
USE_CHIBIOS_CONTRIB = yes
@ -163,6 +208,7 @@ QUANTUM_LIB_SRC += $(STARTUPASM) $(PORTASM) $(OSALASM)
CHIBISRC := $(patsubst $(TOP_DIR)/%,%,$(CHIBISRC))
EXTRAINCDIRS += $(CHIBIOS)/os/license $(CHIBIOS)/os/oslib/include \
$(TOP_DIR)/platforms/chibios/$(BOARD)/configs \
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
$(STREAMSINC) $(CHIBIOS)/os/various $(COMMON_VPATH)
@ -182,6 +228,8 @@ else ifneq ("$(wildcard $(KEYBOARD_PATH_2)/halconf_community.h)","")
USE_CHIBIOS_CONTRIB = yes
else ifneq ("$(wildcard $(KEYBOARD_PATH_1)/halconf_community.h)","")
USE_CHIBIOS_CONTRIB = yes
else ifneq ("$(wildcard $(TOP_DIR)/platforms/chibios/$(BOARD)/configs/halconf_community.h)","")
USE_CHIBIOS_CONTRIB = yes
endif
ifeq ($(strip $(USE_CHIBIOS_CONTRIB)),yes)
@ -194,6 +242,15 @@ endif
# Project, sources and paths
##############################################################################
##############################################################################
# Injected configs
#
ifneq ("$(wildcard $(BOARD_PATH)/configs/config.h)","")
CONFIG_H += $(BOARD_PATH)/configs/config.h
endif
ifneq ("$(wildcard $(BOARD_PATH)/configs/post_config.h)","")
POST_CONFIG_H += $(BOARD_PATH)/configs/post_config.h
endif
##############################################################################
# Compiler settings

6
util/chibios-upgrader.sh
Unescape View File

@ -38,7 +38,11 @@ find_chibi_files() {
local search_path="$1"
shift
local conditions=( "$@" )
find -L "$search_path" -not -path '*/lib/chibios*' -and -not -path '*/lib/ugfx*' -and -not -path '*/util/*' -and \( "${conditions[@]}" \) | sort
for file in $(find -L "$search_path" -not -path '*/lib/chibios*' -and -not -path '*/lib/ugfx*' -and -not -path '*/util/*' -and \( "${conditions[@]}" \) | sort) ; do
if [ -z "$(grep 'include_next' "$file")" ] ; then
echo $file
fi
done
}
revert_chibi_files() {

2
util/travis_compiled_push.sh
Unescape View File

@ -13,7 +13,7 @@ if [[ "$TRAVIS_BRANCH" == "master" && "$TRAVIS_PULL_REQUEST" == "false" ]] ; the
# fix formatting
git checkout master
git diff --diff-filter=AM --name-only -n 1 -z ${TRAVIS_COMMIT_RANGE} | xargs -0 dos2unix
git diff --diff-filter=AM --name-only -n 1 -z ${TRAVIS_COMMIT_RANGE} '*.c' '*.h' '*.cpp' | grep -z -e '^drivers' -e '^quantum' -e '^tests' -e '^tmk_core' | grep -zv -e 'quantum/template' -e 'tmk_core/protocol/usb_hid' | xargs -0 clang-format-7 -i
git diff --diff-filter=AM --name-only -n 1 -z ${TRAVIS_COMMIT_RANGE} '*.c' '*.h' '*.cpp' | grep -z -e '^drivers' -e '^quantum' -e '^tests' -e '^tmk_core' | grep -zv -e 'quantum/template' -e 'tmk_core/protocol/usb_hid' -e 'platforms/chibios' | xargs -0 clang-format-7 -i
git diff --diff-filter=AM --name-only -n 1 -z ${TRAVIS_COMMIT_RANGE} | xargs -0 git add
git commit -m "format code according to conventions [skip ci]" && git push git@github.com:qmk/qmk_firmware.git master

Write Preview
Loading…
Cancel
Save